3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * and Grant Erickson <gerickson@nuovations.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /************************************************************************
13 * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
14 ***********************************************************************/
19 /*-----------------------------------------------------------------------
20 * High Level Configuration Options
21 *----------------------------------------------------------------------*/
22 #define CONFIG_IO64 1 /* Board is Io64 */
23 #define CONFIG_405EX 1 /* Specifc 405EX support*/
24 #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
26 #ifndef CONFIG_SYS_TEXT_BASE
27 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
33 #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
36 * Include common defines/options for all AMCC eval boards
38 #define CONFIG_HOSTNAME io64
39 #define CONFIG_IDENT_STRING " io64 0.02"
40 #include "amcc-common.h"
42 #define CONFIG_BOARD_EARLY_INIT_F
43 #define CONFIG_BOARD_EARLY_INIT_R
44 #define CONFIG_MISC_INIT_R
45 #define CONFIG_LAST_STAGE_INIT
47 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
48 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
49 #define CONFIG_AUTOBOOT_STOP_STR " "
51 /* new uImage format support */
53 #define CONFIG_FIT_VERBOSE
55 /*-----------------------------------------------------------------------
56 * Base addresses -- Note these are effective addresses where the
57 * actual resources get mapped (not physical addresses)
58 *----------------------------------------------------------------------*/
59 #define CONFIG_SYS_FLASH_BASE 0xFC000000
60 #define CONFIG_SYS_NVRAM_BASE 0xF0000000
61 #define CONFIG_SYS_FPGA0_BASE 0xF0100000
62 #define CONFIG_SYS_FPGA1_BASE 0xF0108000
63 #define CONFIG_SYS_LATCH_BASE 0xF0200000
65 /*-----------------------------------------------------------------------
66 * Initial RAM & Stack Pointer Configuration Options
68 * There are traditionally three options for the primordial
69 * (i.e. initial) stack usage on the 405-series:
71 * 1) On-chip Memory (OCM) (i.e. SRAM)
75 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
76 * the latter of which is less than desireable since it requires
77 * setting up the SDRAM and ECC in assembly code.
79 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
80 * select on the External Bus Controller (EBC) and then select a
81 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
82 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
83 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
84 * physical SDRAM to use (3).
85 *-----------------------------------------------------------------------*/
87 #define CONFIG_SYS_INIT_DCACHE_CS 4
89 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
90 #define CONFIG_SYS_INIT_RAM_ADDR \
91 (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
93 #define CONFIG_SYS_INIT_RAM_ADDR \
94 (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
95 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
97 #define CONFIG_SYS_INIT_RAM_SIZE \
99 #define CONFIG_SYS_GBL_DATA_OFFSET \
100 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 * If the data cache is being used for the primordial stack and global
104 * data area, the POST word must be placed somewhere else. The General
105 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
106 * its compare and mask register contents across reset, so it is used
110 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
111 # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
112 # define CONFIG_SYS_POST_WORD_ADDR \
113 (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
115 # define CONFIG_SYS_INIT_EXTRA_SIZE 16
116 # define CONFIG_SYS_INIT_SP_OFFSET \
117 (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
118 # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
119 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
121 /*-----------------------------------------------------------------------
123 *----------------------------------------------------------------------*/
124 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
125 #define CONFIG_SYS_BASE_BAUD 691200
127 /*-----------------------------------------------------------------------
129 *----------------------------------------------------------------------*/
130 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
132 /*-----------------------------------------------------------------------
134 *----------------------------------------------------------------------*/
135 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
136 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
138 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
139 #define CONFIG_SYS_MAX_FLASH_BANKS 1
140 #define CONFIG_SYS_MAX_FLASH_SECT 512
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
146 #define CONFIG_SYS_FLASH_EMPTY_INFO
148 #ifdef CONFIG_ENV_IS_IN_FLASH
149 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
150 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
151 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
153 /* Address and size of Redundant Environment Sector */
154 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
155 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
156 #endif /* CONFIG_ENV_IS_IN_FLASH */
159 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
160 #define CONFIG_BITBANGMII_MULTI
162 #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
163 #define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
165 #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
167 #define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
168 #define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
170 #define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
172 /*-----------------------------------------------------------------------
174 *----------------------------------------------------------------------*/
175 #define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
178 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
180 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
181 * SDRAM Controller DDR autocalibration values and takes a lot longer
182 * to run than Method_B.
183 * (See the Method_A and Method_B algorithm discription in the file:
184 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
185 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
187 * DDR Autocalibration Method_B is the default.
189 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
190 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
191 #undef CONFIG_PPC4xx_DDR_METHOD_A
193 #define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
195 /* DDR1/2 SDRAM Device Control Register Data Values */
196 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
197 SDRAM_RXBAS_SDSZ_128MB | \
198 SDRAM_RXBAS_SDAM_MODE2 | \
199 SDRAM_RXBAS_SDBE_ENABLE)
200 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
201 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
202 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
203 #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
204 SDRAM_MCOPT1_4_BANKS | \
205 SDRAM_MCOPT1_DDR2_TYPE | \
206 SDRAM_MCOPT1_QDEP | \
207 SDRAM_MCOPT1_DCOO_DISABLED)
208 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
209 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
210 SDRAM_MODT_EB0R_ENABLE)
211 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
212 #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
213 SDRAM_CODT_CKLZ_36OHM | \
214 SDRAM_CODT_DQS_1_8_V_DDR2 | \
216 #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
217 #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
218 SDRAM_INITPLR_IMWT_ENCODE(80) | \
219 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
220 #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
221 SDRAM_INITPLR_IMWT_ENCODE(3) | \
222 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
223 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
224 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
225 #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
226 SDRAM_INITPLR_IMWT_ENCODE(2) | \
227 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
228 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
229 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
230 #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
231 SDRAM_INITPLR_IMWT_ENCODE(2) | \
232 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
233 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
234 SDRAM_INITPLR_IMA_ENCODE(0))
235 #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
236 SDRAM_INITPLR_IMWT_ENCODE(2) | \
237 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
238 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
239 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
240 JEDEC_MA_EMR_RTT_75OHM))
241 #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
242 SDRAM_INITPLR_IMWT_ENCODE(2) | \
243 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
244 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
245 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
246 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
247 JEDEC_MA_MR_BLEN_4 | \
248 JEDEC_MA_MR_DLL_RESET))
249 #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
250 SDRAM_INITPLR_IMWT_ENCODE(3) | \
251 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
252 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
253 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
254 #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
255 SDRAM_INITPLR_IMWT_ENCODE(26) | \
256 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
257 #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
258 SDRAM_INITPLR_IMWT_ENCODE(26) | \
259 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
260 #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
261 SDRAM_INITPLR_IMWT_ENCODE(26) | \
262 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
263 #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
264 SDRAM_INITPLR_IMWT_ENCODE(26) | \
265 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
266 #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
267 SDRAM_INITPLR_IMWT_ENCODE(2) | \
268 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
269 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
270 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
271 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
273 #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
274 SDRAM_INITPLR_IMWT_ENCODE(2) | \
275 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
276 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
277 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
278 JEDEC_MA_EMR_RDQS_DISABLE | \
279 JEDEC_MA_EMR_DQS_DISABLE | \
280 JEDEC_MA_EMR_RTT_DISABLED | \
281 JEDEC_MA_EMR_ODS_NORMAL))
282 #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
283 SDRAM_INITPLR_IMWT_ENCODE(2) | \
284 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
285 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
286 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
287 JEDEC_MA_EMR_RDQS_DISABLE | \
288 JEDEC_MA_EMR_DQS_DISABLE | \
289 JEDEC_MA_EMR_RTT_DISABLED | \
290 JEDEC_MA_EMR_ODS_NORMAL))
291 #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
292 #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
293 #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
294 SDRAM_RQDC_RQFD_ENCODE(56))
295 #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
296 #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
297 #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
298 SDRAM_DLCR_DLCS_CONT_DONE | \
299 SDRAM_DLCR_DLCV_ENCODE(165))
300 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
301 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
302 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
303 SDRAM_SDTR1_RTW_2_CLK | \
304 SDRAM_SDTR1_WTWO_1_CLK | \
305 SDRAM_SDTR1_RTRO_1_CLK)
306 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
307 SDRAM_SDTR2_WTR_2_CLK | \
308 SDRAM_SDTR2_XSNR_32_CLK | \
309 SDRAM_SDTR2_WPC_4_CLK | \
310 SDRAM_SDTR2_RPC_2_CLK | \
311 SDRAM_SDTR2_RP_3_CLK | \
312 SDRAM_SDTR2_RRD_2_CLK)
313 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
314 SDRAM_SDTR3_RC_ENCODE(12) | \
316 SDRAM_SDTR3_RFC_ENCODE(21))
317 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
318 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
320 #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
321 SDRAM_MEMODE_RTT_75OHM)
323 /*-----------------------------------------------------------------------
325 *----------------------------------------------------------------------*/
326 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
328 #define CONFIG_PCA9698 1 /* NXP PCA9698 */
330 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
331 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
332 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
333 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
335 /* I2C bootstrap EEPROM */
336 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
337 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
338 #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
340 /* Temp sensor/hwmon/dtt */
341 #define CONFIG_DTT_LM63 1 /* National LM63 */
342 #define CONFIG_DTT_SENSORS { 0x18, 0x4c, 0x4e } /* Sensor addresses */
343 #define CONFIG_DTT_PWM_LOOKUPTABLE \
344 { { 40, 10 }, { 43, 13 }, { 46, 16 }, \
345 { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
346 #define CONFIG_DTT_TACH_LIMIT 0xa10
348 /*-----------------------------------------------------------------------
350 *----------------------------------------------------------------------*/
351 #define CONFIG_M88E1111_PHY 1
352 #define CONFIG_IBM_EMAC4_V4 1
353 #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
354 #define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
356 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
357 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
359 #define CONFIG_HAS_ETH0 1
361 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
362 #define CONFIG_PHY1_ADDR 0x13
364 /* Debug messages for the DDR autocalibration */
365 #define CONFIG_AUTOCALIB "silent\0"
368 * Default environment variables
370 #define CONFIG_EXTRA_ENV_SETTINGS \
371 CONFIG_AMCC_DEF_ENV \
372 CONFIG_AMCC_DEF_ENV_POWERPC \
373 CONFIG_AMCC_DEF_ENV_PPC_OLD \
374 CONFIG_AMCC_DEF_ENV_NOR_UPD \
376 "kernel_addr=fc000000\0" \
377 "fdt_addr=fc1e0000\0" \
378 "ramdisk_addr=fc200000\0" \
379 "pciconfighost=1\0" \
380 "pcie_mode=RP:RP\0" \
384 * Commands additional to the ones defined in amcc-common.h
386 #define CONFIG_CMD_CHIP_CONFIG
387 #define CONFIG_CMD_DTT
389 #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
392 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
393 CONFIG_SYS_POST_CPU | \
394 CONFIG_SYS_POST_ETHER | \
395 CONFIG_SYS_POST_I2C | \
396 CONFIG_SYS_POST_MEMORY_ON | \
397 CONFIG_SYS_POST_UART)
399 /* Define here the base-addresses of the UARTs to test in POST */
400 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
401 CONFIG_SYS_NS16550_COM2 }
403 #define CONFIG_LOGBUFFER
404 #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
406 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
408 /*-----------------------------------------------------------------------
409 * External Bus Controller (EBC) Setup
410 *----------------------------------------------------------------------*/
412 /* Memory Bank 0 (NOR-flash) */
413 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
414 EBC_BXAP_TWT_ENCODE(11) | \
415 EBC_BXAP_BCE_DISABLE | \
416 EBC_BXAP_BCT_2TRANS | \
417 EBC_BXAP_CSN_ENCODE(0) | \
418 EBC_BXAP_OEN_ENCODE(0) | \
419 EBC_BXAP_WBN_ENCODE(1) | \
420 EBC_BXAP_WBF_ENCODE(2) | \
421 EBC_BXAP_TH_ENCODE(2) | \
422 EBC_BXAP_RE_DISABLED | \
423 EBC_BXAP_SOR_NONDELAYED | \
424 EBC_BXAP_BEM_WRITEONLY | \
425 EBC_BXAP_PEN_DISABLED)
426 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
431 /* Memory Bank 1 (NVRAM/Uart) */
432 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
433 EBC_BXAP_FWT_ENCODE(8) | \
434 EBC_BXAP_BWT_ENCODE(4) | \
435 EBC_BXAP_BCE_DISABLE | \
436 EBC_BXAP_BCT_2TRANS | \
437 EBC_BXAP_CSN_ENCODE(0) | \
438 EBC_BXAP_OEN_ENCODE(1) | \
439 EBC_BXAP_WBN_ENCODE(1) | \
440 EBC_BXAP_WBF_ENCODE(1) | \
441 EBC_BXAP_TH_ENCODE(2) | \
442 EBC_BXAP_RE_DISABLED | \
443 EBC_BXAP_SOR_NONDELAYED | \
444 EBC_BXAP_BEM_WRITEONLY | \
445 EBC_BXAP_PEN_DISABLED)
446 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
451 /* Memory Bank 2 (FPGA) */
452 #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
453 EBC_BXAP_TWT_ENCODE(5) | \
454 EBC_BXAP_BCE_DISABLE | \
455 EBC_BXAP_BCT_2TRANS | \
456 EBC_BXAP_CSN_ENCODE(0) | \
457 EBC_BXAP_OEN_ENCODE(2) | \
458 EBC_BXAP_WBN_ENCODE(1) | \
459 EBC_BXAP_WBF_ENCODE(1) | \
460 EBC_BXAP_TH_ENCODE(0) | \
461 EBC_BXAP_RE_DISABLED | \
462 EBC_BXAP_SOR_NONDELAYED | \
463 EBC_BXAP_BEM_WRITEONLY | \
464 EBC_BXAP_PEN_DISABLED)
465 #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
470 /* Memory Bank 3 (Latches) */
471 #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
472 EBC_BXAP_FWT_ENCODE(8) | \
473 EBC_BXAP_BWT_ENCODE(4) | \
474 EBC_BXAP_BCE_DISABLE | \
475 EBC_BXAP_BCT_2TRANS | \
476 EBC_BXAP_CSN_ENCODE(0) | \
477 EBC_BXAP_OEN_ENCODE(1) | \
478 EBC_BXAP_WBN_ENCODE(1) | \
479 EBC_BXAP_WBF_ENCODE(1) | \
480 EBC_BXAP_TH_ENCODE(2) | \
481 EBC_BXAP_RE_DISABLED | \
482 EBC_BXAP_SOR_NONDELAYED | \
483 EBC_BXAP_BEM_WRITEONLY | \
484 EBC_BXAP_PEN_DISABLED)
485 #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
490 /* EBC peripherals */
492 #define CONFIG_SYS_FPGA_BASE(k) \
493 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
495 #define CONFIG_SYS_FPGA_DONE(k) \
496 (k ? 0x0040 : 0x0080)
498 #define CONFIG_SYS_FPGA_COUNT 2
500 #define CONFIG_SYS_FPGA_PTR { \
501 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
502 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
504 #define CONFIG_SYS_FPGA_COMMON
506 #define CONFIG_SYS_LATCH0_RESET 0xffff
507 #define CONFIG_SYS_LATCH0_BOOT 0xffff
508 #define CONFIG_SYS_LATCH1_RESET 0xffbf
509 #define CONFIG_SYS_LATCH1_BOOT 0xffff
511 /*-----------------------------------------------------------------------
513 *----------------------------------------------------------------------*/
514 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
517 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
518 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
519 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
520 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
521 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
522 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
523 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
524 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
525 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
526 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
527 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
528 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
529 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
530 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
531 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
532 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
533 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
534 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
535 {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
536 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
537 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
538 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
539 {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
540 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
541 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
542 {GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
543 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
544 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
545 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
546 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
547 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
548 {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
552 #define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
553 #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
555 #endif /* __CONFIG_H */