3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * This file contains the configuration parameters for the INCA-IP board.
31 #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
32 #define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
34 /* allowed values: 100000000 and 150000000 */
35 #define CPU_CLOCK_RATE 150000000 /* 150 MHz clock for the MIPS core */
37 #define CONFIG_BAUDRATE 115200
39 #define CFG_SDRAM_BASE 0x80000000
41 #define CFG_MALLOC_LEN 128*1024
43 #define CFG_BOOTPARAMS_LEN 128*1024
46 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
48 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF)
49 #include <cmd_confdefs.h>
52 * Miscellaneous configurable options
54 #define CFG_LONGHELP /* undef to save memory */
55 #define CFG_PROMPT "INCA-IP # " /* Monitor Command Prompt */
56 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
57 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
58 #define CFG_HZ (CPU_CLOCK_RATE/2)
59 #define CFG_MAXARGS 16 /* max number of command args*/
61 #define CFG_LOAD_ADDR 0x80100000 /* default load address */
63 #define CFG_MEMTEST_START 0x80200000
64 #define CFG_MEMTEST_END 0x80800000
66 /*-----------------------------------------------------------------------
67 * FLASH and environment organization
69 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
70 #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
72 #define PHYS_FLASH_1 0xb0000000 /* Flash Bank #1 */
73 #define PHYS_FLASH_2 0xb0800000 /* Flash Bank #2 */
75 /* The following #defines are needed to get flash environment right */
76 #define CFG_MONITOR_BASE TEXT_BASE
77 #define CFG_MONITOR_LEN (192 << 10)
79 #define CFG_INIT_SP_OFFSET 0x400000
81 #define CFG_FLASH_BASE PHYS_FLASH_1
83 /* timeout values are in ticks */
84 #define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
85 #define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
87 #define CFG_ENV_IS_IN_FLASH 1
89 /* Address and size of Primary Environment Sector */
90 #define CFG_ENV_ADDR 0xB0030000
91 #define CFG_ENV_SIZE 0x10000
93 #define CONFIG_FLASH_16BIT
95 #define CONFIG_NR_DRAM_BANKS 1
97 #define CONFIG_INCA_IP_SWITCH
98 #define CONFIG_NET_MULTI
100 /*-----------------------------------------------------------------------
101 * Cache Configuration
103 #define CFG_DCACHE_SIZE 4096
104 #define CFG_ICACHE_SIZE 4096
105 #define CFG_CACHELINE_SIZE 16
107 #endif /* __CONFIG_H */