include/configs/imx8ulp_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 NXP
   4  */
   5
   6 #ifndef __IMX8ULP_EVK_H
   7 #define __IMX8ULP_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <asm/arch/imx-regs.h>
  11
  12 #define CONFIG_SYS_BOOTM_LEN            (SZ_64M)
  13 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  14 #define CONFIG_SYS_UBOOT_BASE   (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  15
  16 #ifdef CONFIG_SPL_BUILD
  17 #define CONFIG_MALLOC_F_ADDR            0x22040000
  18
  19
  20 #endif
  21
  22 /* ENET Config */
  23 #if defined(CONFIG_FEC_MXC)
  24 #define PHY_ANEG_TIMEOUT                20000
  25
  26 #define CONFIG_FEC_MXC_PHYADDR          1
  27 #endif
  28
  29 #ifdef CONFIG_DISTRO_DEFAULTS
  30 #define BOOT_TARGET_DEVICES(func) \
  31         func(MMC, mmc, 0)
  32
  33 #include <config_distro_bootcmd.h>
  34 #else
  35 #define BOOTENV
  36 #endif
  37
  38 /* Initial environment variables */
  39 #define CONFIG_EXTRA_ENV_SETTINGS               \
  40         BOOTENV \
  41         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  42         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  43         "image=Image\0" \
  44         "console=ttyLP1,115200 earlycon\0" \
  45         "fdt_addr_r=0x83000000\0"                       \
  46         "boot_fit=no\0" \
  47         "fdtfile=imx8ulp-evk.dtb\0" \
  48         "initrd_addr=0x83800000\0"              \
  49         "bootm_size=0x10000000\0" \
  50         "mmcpart=1\0" \
  51         "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
  52
  53 /* Link Definitions */
  54
  55 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  56 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  57
  58
  59 #define CONFIG_SYS_SDRAM_BASE           0x80000000
  60 #define PHYS_SDRAM                      0x80000000
  61 #define PHYS_SDRAM_SIZE                 0x80000000 /* 2GB DDR */
  62
  63 /* Using ULP WDOG for reset */
  64 #define WDOG_BASE_ADDR                  WDG3_RBASE
  65 #endif