board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks
[platform/kernel/u-boot.git] / include / configs / imx8ulp_evk.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2020 NXP
4  */
5
6 #ifndef __IMX8ULP_EVK_H
7 #define __IMX8ULP_EVK_H
8
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
11
12 #define CONFIG_SYS_BOOTM_LEN            (SZ_64M)
13 #define CONFIG_SPL_MAX_SIZE             (148 * 1024)
14 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
15 #define CONFIG_SYS_UBOOT_BASE   (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
16
17 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_SPL_STACK                0x22050000
19 #define CONFIG_SPL_BSS_START_ADDR       0x22048000
20 #define CONFIG_SPL_BSS_MAX_SIZE         0x2000  /* 8 KB */
21 #define CONFIG_SYS_SPL_MALLOC_START     0x22040000
22 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x8000  /* 32 KB */
23
24 #define CONFIG_MALLOC_F_ADDR            0x22040000
25
26 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
27
28 #endif
29
30 /* ENET Config */
31 #if defined(CONFIG_FEC_MXC)
32 #define PHY_ANEG_TIMEOUT                20000
33
34 #define CONFIG_FEC_MXC_PHYADDR          1
35 #endif
36
37 #ifdef CONFIG_DISTRO_DEFAULTS
38 #define BOOT_TARGET_DEVICES(func) \
39         func(MMC, mmc, 0)
40
41 #include <config_distro_bootcmd.h>
42 #else
43 #define BOOTENV
44 #endif
45
46 /* Initial environment variables */
47 #define CONFIG_EXTRA_ENV_SETTINGS               \
48         BOOTENV \
49         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
50         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
51         "image=Image\0" \
52         "console=ttyLP1,115200 earlycon\0" \
53         "fdt_addr_r=0x83000000\0"                       \
54         "boot_fit=no\0" \
55         "fdtfile=imx8ulp-evk.dtb\0" \
56         "initrd_addr=0x83800000\0"              \
57         "bootm_size=0x10000000\0" \
58         "mmcpart=1\0" \
59         "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
60
61 /* Link Definitions */
62
63 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
64 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
65 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
66 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
67
68
69 #define CONFIG_SYS_SDRAM_BASE           0x80000000
70 #define PHYS_SDRAM                      0x80000000
71 #define PHYS_SDRAM_SIZE                 0x80000000 /* 2GB DDR */
72
73 /* Monitor Command Prompt */
74 #define CONFIG_SYS_CBSIZE               2048
75 #define CONFIG_SYS_MAXARGS              64
76 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
77 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
78
79 /* Using ULP WDOG for reset */
80 #define WDOG_BASE_ADDR                  WDG3_RBASE
81 #endif