1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8QXP_MEK_H
7 #define __IMX8QXP_MEK_H
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
13 #ifdef CONFIG_SPL_BUILD
14 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
15 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
19 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
20 #define CONFIG_SPL_STACK 0x013E000
21 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
22 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
23 #define CONFIG_SYS_SPL_MALLOC_START 0x00120000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
25 #define CONFIG_SERIAL_LPUART_BASE 0x5a060000
26 #define CONFIG_MALLOC_F_ADDR 0x00120000
28 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
32 #define CONFIG_OF_EMBED
35 #define CONFIG_REMAKE_ELF
37 /* Flat Device Tree Definitions */
38 #define CONFIG_OF_BOARD_SETUP
40 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
41 #define USDHC1_BASE_ADDR 0x5B010000
42 #define USDHC2_BASE_ADDR 0x5B020000
44 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
46 #ifdef CONFIG_AHAB_BOOT
47 #define AHAB_ENV "sec_boot=yes\0"
49 #define AHAB_ENV "sec_boot=no\0"
52 /* Initial environment variables */
53 #define CONFIG_EXTRA_ENV_SETTINGS \
59 "fdt_addr=0x83000000\0" \
60 "fdt_high=0xffffffffffffffff\0" \
62 "fdt_file=undefined\0" \
63 "initrd_addr=0x83800000\0" \
64 "initrd_high=0xffffffffffffffff\0" \
65 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
66 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
67 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
68 "mmcautodetect=yes\0" \
69 "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
70 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
71 "bootscript=echo Running bootscript from mmc ...; " \
73 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
74 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
75 "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
76 "auth_os=auth_cntr ${cntr_addr}\0" \
77 "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
78 "mmcboot=echo Booting from mmc ...; " \
80 "if test ${sec_boot} = yes; then " \
81 "if run auth_os; then " \
84 "echo ERR: failed to authenticate; " \
87 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
88 "if run loadfdt; then " \
91 "echo WARN: Cannot load the DT; " \
94 "echo wait for boot; " \
97 "netargs=setenv bootargs console=${console},${baudrate} " \
99 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
100 "netboot=echo Booting from net ...; " \
102 "if test ${ip_dyn} = yes; then " \
103 "setenv get_cmd dhcp; " \
105 "setenv get_cmd tftp; " \
107 "if test ${sec_boot} = yes; then " \
108 "${get_cmd} ${cntr_addr} ${cntr_file}; " \
109 "if run auth_os; then " \
112 "echo ERR: failed to authenticate; " \
115 "${get_cmd} ${loadaddr} ${image}; " \
116 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
117 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
120 "echo WARN: Cannot load the DT; " \
127 #define CONFIG_BOOTCOMMAND \
128 "mmc dev ${mmcdev}; if mmc rescan; then " \
129 "if run loadbootscript; then " \
132 "if test ${sec_boot} = yes; then " \
133 "if run loadcntr; then " \
135 "else run netboot; " \
138 "if run loadimage; then " \
140 "else run netboot; " \
144 "else booti ${loadaddr} - ${fdt_addr}; fi"
146 /* Link Definitions */
147 #define CONFIG_LOADADDR 0x80280000
149 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
151 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
153 /* Default environment is in SD */
155 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
157 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
158 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
159 #define CONFIG_SYS_FSL_USDHC_NUM 2
161 /* Size of malloc() pool */
162 #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
164 #define CONFIG_SYS_SDRAM_BASE 0x80000000
165 #define PHYS_SDRAM_1 0x80000000
166 #define PHYS_SDRAM_2 0x880000000
167 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
168 /* LPDDR4 board total DDR is 3GB */
169 #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
171 /* Generic Timer Definitions */
172 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
174 #ifndef CONFIG_DM_PCA953X
175 #define CONFIG_PCA953X
179 #define CONFIG_FEC_XCV_TYPE RGMII
180 #define FEC_QUIRK_ENET_MAC
182 /* Misc configuration */
183 #define CONFIG_SYS_CBSIZE 2048
184 #define CONFIG_SYS_MAXARGS 64
185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
187 #endif /* __IMX8QXP_MEK_H */