1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
6 #ifndef __IMX8QM_ROM7720_H
7 #define __IMX8QM_ROM7720_H
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
12 #define CONFIG_REMAKE_ELF
14 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
15 #define CONFIG_SPL_BSS_START_ADDR 0x00128000
16 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
18 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
19 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
20 #define USDHC1_BASE_ADDR 0x5B010000
21 #define USDHC2_BASE_ADDR 0x5B020000
22 #define USDHC3_BASE_ADDR 0x5B030000
28 "m4_0_image=m4_0.bin\0" \
29 "m4_1_image=m4_1.bin\0" \
30 "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
31 "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
32 "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
33 "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
35 #ifdef CONFIG_NAND_BOOT
36 #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
38 #define MFG_NAND_PARTITION ""
41 #define CONFIG_MFG_ENV_SETTINGS \
42 "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
44 "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
45 "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
46 "g_mass_storage.iSerialNumber=\"\" "\
50 "initrd_addr=0x83800000\0" \
51 "initrd_high=0xffffffffffffffff\0" \
52 "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
54 /* Initial environment variables */
55 #define CONFIG_EXTRA_ENV_SETTINGS \
56 CONFIG_MFG_ENV_SETTINGS \
62 "fdt_addr=0x83000000\0" \
64 "fdt_file=imx8qm-rom7720-a1.dtb\0" \
65 "initrd_addr=0x83800000\0" \
66 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
68 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
69 "mmcautodetect=yes\0" \
70 "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
71 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
72 "bootscript=echo Running bootscript from mmc ...; " \
74 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
75 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
76 "mmcboot=echo Booting from mmc ...; " \
78 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
79 "if run loadfdt; then " \
80 "booti ${loadaddr} - ${fdt_addr}; " \
82 "echo WARN: Cannot load the DT; " \
85 "echo wait for boot; " \
87 "netargs=setenv bootargs console=${console},${baudrate} " \
89 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
90 "netboot=echo Booting from net ...; " \
92 "if test ${ip_dyn} = yes; then " \
93 "setenv get_cmd dhcp; " \
95 "setenv get_cmd tftp; " \
97 "${get_cmd} ${loadaddr} ${image}; " \
98 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
100 "booti ${loadaddr} - ${fdt_addr}; " \
102 "echo WARN: Cannot load the DT; " \
108 /* Link Definitions */
110 #define CONFIG_SYS_INIT_SP_ADDR 0x80200000
112 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board,
113 * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
114 * USDHC2 is for SD, USDHC3 is for SD on base board
116 #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
117 #define CONFIG_SYS_FSL_USDHC_NUM 3
119 #define CONFIG_SYS_SDRAM_BASE 0x80000000
120 #define PHYS_SDRAM_1 0x80000000
121 #define PHYS_SDRAM_2 0x880000000
122 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
123 /* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4 GB */
124 #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
126 /* Generic Timer Definitions */
127 #define COUNTER_FREQUENCY 8000000 /* 8MHz */
130 #define CONFIG_FEC_XCV_TYPE RGMII
132 #include <linux/stringify.h>
133 #endif /* __IMX8QM_ROM7720_H */