1 /* SPDX-License-Identifier: GPL-2.0+ */
6 #ifndef __IMX8M_PHANBELL_H
7 #define __IMX8M_PHANBELL_H
9 #include <linux/sizes.h>
10 #include <asm/arch/imx-regs.h>
12 #define CONFIG_SPL_MAX_SIZE (172 * 1024)
13 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
14 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
17 #ifdef CONFIG_SPL_BUILD
18 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
19 #define CONFIG_SPL_WATCHDOG
20 #define CONFIG_SPL_DRIVERS_MISC
21 #define CONFIG_SPL_POWER
22 #define CONFIG_SPL_I2C
23 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
24 #define CONFIG_SPL_STACK 0x187FF0
25 #define CONFIG_SPL_LIBCOMMON_SUPPORT
26 #define CONFIG_SPL_LIBGENERIC_SUPPORT
27 #define CONFIG_SPL_GPIO
28 #define CONFIG_SPL_MMC
29 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
30 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
31 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
32 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
33 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
35 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
36 #define CONFIG_MALLOC_F_ADDR 0x182000
37 /* For RAW image gives a error info not panic */
38 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
43 #define CONFIG_REMAKE_ELF
47 #if defined(CONFIG_CMD_NET)
49 #define CONFIG_ETHPRIME "FEC"
51 #define CONFIG_FEC_XCV_TYPE RGMII
52 #define CONFIG_FEC_MXC_PHYADDR 0
53 #define FEC_QUIRK_ENET_MAC
55 #define CONFIG_PHY_GIGE
56 #define IMX_FEC_BASE 0x30BE0000
61 #define CONFIG_MFG_ENV_SETTINGS \
62 "initrd_addr=0x43800000\0" \
63 "initrd_high=0xffffffff\0" \
65 /* Initial environment variables */
66 #define CONFIG_EXTRA_ENV_SETTINGS \
67 CONFIG_MFG_ENV_SETTINGS \
70 "console=ttymxc0,115200\0" \
71 "fdt_addr=0x43000000\0" \
72 "fdt_high=0xffffffffffffffff\0" \
74 "fdt_file=imx8mq-phanbell.dtb\0" \
75 "initrd_addr=0x43800000\0" \
76 "initrd_high=0xffffffffffffffff\0" \
77 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
78 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
79 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
80 "mmcautodetect=yes\0" \
81 "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
82 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
83 "bootscript=echo Running bootscript from mmc ...; " \
85 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
86 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
87 "mmcboot=echo Booting from mmc ...; " \
89 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
90 "if run loadfdt; then " \
91 "booti ${loadaddr} - ${fdt_addr}; " \
93 "echo WARN: Cannot load the DT; " \
96 "echo wait for boot; " \
98 "netargs=setenv bootargs console=${console} " \
100 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
101 "netboot=echo Booting from net ...; " \
103 "if test ${ip_dyn} = yes; then " \
104 "setenv get_cmd dhcp; " \
106 "setenv get_cmd tftp; " \
108 "${get_cmd} ${loadaddr} ${image}; " \
109 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
110 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
111 "booti ${loadaddr} - ${fdt_addr}; " \
113 "echo WARN: Cannot load the DT; " \
119 #define CONFIG_BOOTCOMMAND \
120 "mmc dev ${mmcdev}; if mmc rescan; then " \
121 "if run loadbootscript; then " \
124 "if run loadimage; then " \
126 "else run netboot; " \
129 "else booti ${loadaddr} - ${fdt_addr}; fi"
131 /* Link Definitions */
133 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
134 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
135 #define CONFIG_SYS_INIT_SP_OFFSET \
136 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
137 #define CONFIG_SYS_INIT_SP_ADDR \
138 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
140 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
142 #define CONFIG_SYS_SDRAM_BASE 0x40000000
143 #define PHYS_SDRAM 0x40000000
144 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
146 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
147 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
148 (PHYS_SDRAM_SIZE >> 1))
150 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
152 /* Monitor Command Prompt */
153 #define CONFIG_SYS_CBSIZE 1024
154 #define CONFIG_SYS_MAXARGS 64
155 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
156 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
157 sizeof(CONFIG_SYS_PROMPT) + 16)
159 #define CONFIG_IMX_BOOTAUX
161 #define CONFIG_SYS_FSL_USDHC_NUM 2
162 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
164 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
166 #define CONFIG_MXC_GPIO
168 #define CONFIG_OF_SYSTEM_SETUP