include/configs/imx8mq_phanbell.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2020 NXP
   4  */
   5
   6 #ifndef __IMX8M_PHANBELL_H
   7 #define __IMX8M_PHANBELL_H
   8
   9 #include <linux/sizes.h>
  10 #include <asm/arch/imx-regs.h>
  11
  12 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  13
  14 #ifdef CONFIG_SPL_BUILD
  15 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  16 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  17
  18 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  19 #define CONFIG_MALLOC_F_ADDR            0x182000
  20 /* For RAW image gives a error info not panic */
  21 #endif
  22
  23 /* ENET Config */
  24 /* ENET1 */
  25 #if defined(CONFIG_CMD_NET)
  26 #define CONFIG_FEC_MXC_PHYADDR          0
  27 #endif
  28
  29 #define CONFIG_MFG_ENV_SETTINGS \
  30         "initrd_addr=0x43800000\0" \
  31         "initrd_high=0xffffffff\0" \
  32
  33 /* Initial environment variables */
  34 #define CONFIG_EXTRA_ENV_SETTINGS               \
  35         CONFIG_MFG_ENV_SETTINGS \
  36         "script=boot.scr\0" \
  37         "image=Image\0" \
  38         "console=ttymxc0,115200\0" \
  39         "fdt_addr=0x43000000\0"                 \
  40         "fdt_high=0xffffffffffffffff\0"         \
  41         "boot_fdt=try\0" \
  42         "fdt_file=imx8mq-phanbell.dtb\0" \
  43         "initrd_addr=0x43800000\0"              \
  44         "initrd_high=0xffffffffffffffff\0" \
  45         "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  46         "mmcpart=1\0" \
  47         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  48         "mmcautodetect=yes\0" \
  49         "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  50         "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  51         "bootscript=echo Running bootscript from mmc ...; " \
  52                 "source\0" \
  53         "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  54         "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  55         "mmcboot=echo Booting from mmc ...; " \
  56                 "run mmcargs; " \
  57                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  58                         "if run loadfdt; then " \
  59                                 "booti ${loadaddr} - ${fdt_addr}; " \
  60                         "else " \
  61                                 "echo WARN: Cannot load the DT; " \
  62                         "fi; " \
  63                 "else " \
  64                         "echo wait for boot; " \
  65                 "fi;\0" \
  66         "netargs=setenv bootargs console=${console} " \
  67                 "root=/dev/nfs " \
  68                 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  69         "netboot=echo Booting from net ...; " \
  70                 "run netargs;  " \
  71                 "if test ${ip_dyn} = yes; then " \
  72                         "setenv get_cmd dhcp; " \
  73                 "else " \
  74                         "setenv get_cmd tftp; " \
  75                 "fi; " \
  76                 "${get_cmd} ${loadaddr} ${image}; " \
  77                 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  78                         "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  79                                 "booti ${loadaddr} - ${fdt_addr}; " \
  80                         "else " \
  81                                 "echo WARN: Cannot load the DT; " \
  82                         "fi; " \
  83                 "else " \
  84                         "booti; " \
  85                 "fi;\0"
  86
  87 /* Link Definitions */
  88
  89 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  90 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  91
  92
  93 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  94 #define PHYS_SDRAM                      0x40000000
  95 #define PHYS_SDRAM_SIZE                 0x40000000 /* 1GB DDR */
  96
  97 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(1)
  98
  99 #define CONFIG_SYS_FSL_USDHC_NUM        2
 100 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 101
 102 #endif