1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
13 #define CONFIG_SYS_BOOTM_LEN (64 * SZ_1M)
15 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
20 #ifdef CONFIG_SPL_BUILD
21 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
22 #define CONFIG_SPL_STACK 0x187FF0
23 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
24 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
25 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
26 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
27 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
29 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
30 #define CONFIG_MALLOC_F_ADDR 0x182000
31 /* For RAW image gives a error info not panic */
32 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
36 #define CONFIG_POWER_PFUZE100
37 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
40 #define CONFIG_REMAKE_ELF
44 #if defined(CONFIG_CMD_NET)
45 #define CONFIG_ETHPRIME "FEC"
47 #define CONFIG_FEC_XCV_TYPE RGMII
48 #define CONFIG_FEC_MXC_PHYADDR 0
49 #define FEC_QUIRK_ENET_MAC
51 #define IMX_FEC_BASE 0x30BE0000
54 #ifndef CONFIG_SPL_BUILD
55 #define BOOT_TARGET_DEVICES(func) \
60 #include <config_distro_bootcmd.h>
63 /* Initial environment variables */
64 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "scriptaddr=0x43500000\0" \
67 "kernel_addr_r=0x40880000\0" \
69 "console=ttymxc0,115200\0" \
70 "fdt_addr=0x43000000\0" \
72 "fdt_file=imx8mq-evk.dtb\0" \
73 "initrd_addr=0x43800000\0" \
74 "bootm_size=0x10000000\0" \
75 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
76 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
78 /* Link Definitions */
80 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
81 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
82 #define CONFIG_SYS_INIT_SP_OFFSET \
83 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
84 #define CONFIG_SYS_INIT_SP_ADDR \
85 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
87 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
89 #define CONFIG_SYS_SDRAM_BASE 0x40000000
90 #define PHYS_SDRAM 0x40000000
91 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
93 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
95 /* Monitor Command Prompt */
96 #define CONFIG_SYS_CBSIZE 1024
97 #define CONFIG_SYS_MAXARGS 64
98 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
99 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
100 sizeof(CONFIG_SYS_PROMPT) + 16)
102 #define CONFIG_SYS_FSL_USDHC_NUM 2
103 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
105 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
107 #define CONFIG_MXC_GPIO
109 #define CONFIG_OF_SYSTEM_SETUP