include/configs/imx8mq_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_EVK_H
   7 #define __IMX8M_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (64 * SZ_1M)
  14
  15 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  16 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  17
  18 #ifdef CONFIG_SPL_BUILD
  19 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  20 #define CONFIG_SPL_STACK                0x187FF0
  21 #define CONFIG_SPL_BSS_START_ADDR      0x00180000
  22 #define CONFIG_SPL_BSS_MAX_SIZE        0x2000   /* 8 KB */
  23 #define CONFIG_SYS_SPL_MALLOC_START    0x42200000
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000   /* 512 KB */
  25 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  26
  27 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  28 #define CONFIG_MALLOC_F_ADDR            0x182000
  29 /* For RAW image gives a error info not panic */
  30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  31
  32 #define CONFIG_POWER_PFUZE100
  33 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  34 #endif
  35
  36 /* ENET Config */
  37 /* ENET1 */
  38 #if defined(CONFIG_CMD_NET)
  39 #define CONFIG_FEC_MXC_PHYADDR          0
  40 #endif
  41
  42 #ifndef CONFIG_SPL_BUILD
  43 #define BOOT_TARGET_DEVICES(func) \
  44        func(MMC, mmc, 0) \
  45        func(MMC, mmc, 1) \
  46        func(DHCP, dhcp, na)
  47
  48 #include <config_distro_bootcmd.h>
  49 #endif
  50
  51 /* Initial environment variables */
  52 #define CONFIG_EXTRA_ENV_SETTINGS               \
  53         BOOTENV \
  54         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  55         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  56         "image=Image\0" \
  57         "console=ttymxc0,115200\0" \
  58         "fdt_addr_r=0x43000000\0"                       \
  59         "boot_fdt=try\0" \
  60         "fdtfile=imx8mq-evk.dtb\0" \
  61         "initrd_addr=0x43800000\0"              \
  62         "bootm_size=0x10000000\0" \
  63         "mmcpart=1\0" \
  64         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  65
  66 /* Link Definitions */
  67
  68 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  69 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  70 #define CONFIG_SYS_INIT_SP_OFFSET \
  71         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  72 #define CONFIG_SYS_INIT_SP_ADDR \
  73         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  74
  75
  76 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  77 #define PHYS_SDRAM                      0x40000000
  78 #define PHYS_SDRAM_SIZE                 0xC0000000 /* 3GB DDR */
  79
  80 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(1)
  81
  82 /* Monitor Command Prompt */
  83 #define CONFIG_SYS_CBSIZE               1024
  84 #define CONFIG_SYS_MAXARGS              64
  85 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  86 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  87                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  88
  89 #define CONFIG_SYS_FSL_USDHC_NUM        2
  90 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  91
  92 #endif