include/configs/imx8mq_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_EVK_H
   7 #define __IMX8M_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #ifdef CONFIG_SPL_BUILD
  14 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  15 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  16
  17 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  18 #define CFG_MALLOC_F_ADDR               0x182000
  19 /* For RAW image gives a error info not panic */
  20
  21 #define CFG_POWER_PFUZE100_I2C_ADDR 0x08
  22 #endif
  23
  24 /* ENET Config */
  25 /* ENET1 */
  26 #if defined(CONFIG_CMD_NET)
  27 #define CFG_FEC_MXC_PHYADDR          0
  28 #endif
  29
  30 #define BOOT_TARGET_DEVICES(func) \
  31        func(MMC, mmc, 0) \
  32        func(MMC, mmc, 1) \
  33        func(DHCP, dhcp, na)
  34
  35 #include <config_distro_bootcmd.h>
  36
  37 /* Initial environment variables */
  38 #define CFG_EXTRA_ENV_SETTINGS          \
  39         BOOTENV \
  40         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  41         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  42         "image=Image\0" \
  43         "console=ttymxc0,115200\0" \
  44         "fdt_addr_r=0x43000000\0"                       \
  45         "boot_fdt=try\0" \
  46         "fdtfile=imx8mq-evk.dtb\0" \
  47         "initrd_addr=0x43800000\0"              \
  48         "bootm_size=0x10000000\0" \
  49         "mmcpart=1\0" \
  50         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  51
  52 /* Link Definitions */
  53
  54 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
  55 #define CFG_SYS_INIT_RAM_SIZE        0x80000
  56
  57
  58 #define CFG_SYS_SDRAM_BASE           0x40000000
  59 #define PHYS_SDRAM                      0x40000000
  60 #define PHYS_SDRAM_SIZE                 0xC0000000 /* 3GB DDR */
  61
  62 #define CFG_MXC_UART_BASE               UART_BASE_ADDR(1)
  63
  64 #define CFG_SYS_FSL_USDHC_NUM   2
  65 #define CFG_SYS_FSL_ESDHC_ADDR       0
  66
  67 #endif