1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
13 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
15 #define CONFIG_SPL_MAX_SIZE (124 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
20 #ifdef CONFIG_SPL_BUILD
21 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
22 #define CONFIG_SPL_WATCHDOG
23 #define CONFIG_SPL_DRIVERS_MISC
24 #define CONFIG_SPL_POWER
25 #define CONFIG_SPL_I2C
26 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
27 #define CONFIG_SPL_STACK 0x187FF0
28 #define CONFIG_SPL_LIBCOMMON_SUPPORT
29 #define CONFIG_SPL_LIBGENERIC_SUPPORT
30 #define CONFIG_SPL_GPIO
31 #define CONFIG_SPL_MMC
32 #define CONFIG_SPL_BSS_START_ADDR 0x00180000
33 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
34 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
35 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
36 #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
38 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
39 #define CONFIG_MALLOC_F_ADDR 0x182000
40 /* For RAW image gives a error info not panic */
41 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
45 #define CONFIG_POWER_PFUZE100
46 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
49 #define CONFIG_REMAKE_ELF
53 #if defined(CONFIG_CMD_NET)
55 #define CONFIG_ETHPRIME "FEC"
57 #define CONFIG_FEC_MXC
58 #define CONFIG_FEC_XCV_TYPE RGMII
59 #define CONFIG_FEC_MXC_PHYADDR 0
60 #define FEC_QUIRK_ENET_MAC
62 #define CONFIG_PHY_GIGE
63 #define IMX_FEC_BASE 0x30BE0000
66 #ifndef CONFIG_SPL_BUILD
67 #define BOOT_TARGET_DEVICES(func) \
72 #include <config_distro_bootcmd.h>
75 /* Initial environment variables */
76 #define CONFIG_EXTRA_ENV_SETTINGS \
78 "scriptaddr=0x43500000\0" \
79 "kernel_addr_r=0x40880000\0" \
81 "console=ttymxc0,115200\0" \
82 "fdt_addr=0x43000000\0" \
84 "fdt_file=imx8mq-evk.dtb\0" \
85 "initrd_addr=0x43800000\0" \
86 "bootm_size=0x10000000\0" \
87 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
88 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
90 /* Link Definitions */
92 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
93 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
94 #define CONFIG_SYS_INIT_SP_OFFSET \
95 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
96 #define CONFIG_SYS_INIT_SP_ADDR \
97 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
99 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
101 #define CONFIG_SYS_SDRAM_BASE 0x40000000
102 #define PHYS_SDRAM 0x40000000
103 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
105 #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
107 /* Monitor Command Prompt */
108 #undef CONFIG_SYS_PROMPT
109 #define CONFIG_SYS_PROMPT "u-boot=> "
110 #define CONFIG_SYS_CBSIZE 1024
111 #define CONFIG_SYS_MAXARGS 64
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
114 sizeof(CONFIG_SYS_PROMPT) + 16)
116 #define CONFIG_IMX_BOOTAUX
118 #define CONFIG_SYS_FSL_USDHC_NUM 2
119 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
121 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
123 #define CONFIG_MXC_GPIO
125 #define CONFIG_OF_SYSTEM_SETUP