include/configs/imx8mq_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_EVK_H
   7 #define __IMX8M_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (64 * SZ_1M)
  14
  15 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
  16 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  17
  18 #ifdef CONFIG_SPL_BUILD
  19 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  20 #define CONFIG_SPL_STACK                0x187FF0
  21 #define CONFIG_SPL_BSS_START_ADDR      0x00180000
  22 #define CONFIG_SPL_BSS_MAX_SIZE        0x2000   /* 8 KB */
  23 #define CONFIG_SYS_SPL_MALLOC_START    0x42200000
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000   /* 512 KB */
  25 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  26
  27 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  28 #define CONFIG_MALLOC_F_ADDR            0x182000
  29 /* For RAW image gives a error info not panic */
  30 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  31
  32 #undef CONFIG_DM_MMC
  33
  34 #define CONFIG_POWER_PFUZE100
  35 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  36 #endif
  37
  38 /* ENET Config */
  39 /* ENET1 */
  40 #if defined(CONFIG_CMD_NET)
  41 #define CONFIG_FEC_MXC_PHYADDR          0
  42 #define FEC_QUIRK_ENET_MAC
  43
  44 #define IMX_FEC_BASE                    0x30BE0000
  45 #endif
  46
  47 #ifndef CONFIG_SPL_BUILD
  48 #define BOOT_TARGET_DEVICES(func) \
  49        func(MMC, mmc, 0) \
  50        func(MMC, mmc, 1) \
  51        func(DHCP, dhcp, na)
  52
  53 #include <config_distro_bootcmd.h>
  54 #endif
  55
  56 /* Initial environment variables */
  57 #define CONFIG_EXTRA_ENV_SETTINGS               \
  58         BOOTENV \
  59         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  60         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  61         "image=Image\0" \
  62         "console=ttymxc0,115200\0" \
  63         "fdt_addr_r=0x43000000\0"                       \
  64         "boot_fdt=try\0" \
  65         "fdtfile=imx8mq-evk.dtb\0" \
  66         "initrd_addr=0x43800000\0"              \
  67         "bootm_size=0x10000000\0" \
  68         "mmcpart=1\0" \
  69         "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  70
  71 /* Link Definitions */
  72
  73 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  74 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  75 #define CONFIG_SYS_INIT_SP_OFFSET \
  76         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  77 #define CONFIG_SYS_INIT_SP_ADDR \
  78         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  79
  80 #define CONFIG_MMCROOT                  "/dev/mmcblk1p2"  /* USDHC2 */
  81
  82 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  83 #define PHYS_SDRAM                      0x40000000
  84 #define PHYS_SDRAM_SIZE                 0xC0000000 /* 3GB DDR */
  85
  86 #define CONFIG_MXC_UART_BASE            UART1_BASE_ADDR
  87
  88 /* Monitor Command Prompt */
  89 #define CONFIG_SYS_CBSIZE               1024
  90 #define CONFIG_SYS_MAXARGS              64
  91 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  92 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  93                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  94
  95 #define CONFIG_SYS_FSL_USDHC_NUM        2
  96 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  97
  98 #endif