include/configs/imx8mq_cm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #ifndef __IMX8M_CM_H
   7 #define __IMX8M_CM_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
  14
  15 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  16
  17 #ifdef CONFIG_SPL_BUILD
  18 #define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
  19
  20 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  21 #define CONFIG_MALLOC_F_ADDR            0x182000
  22 /* For RAW image gives a error info not panic */
  23
  24 #endif
  25
  26 /* ENET Config */
  27 /* ENET1 */
  28
  29 #define BOOT_TARGET_DEVICES(func) \
  30                 func(MMC, mmc, 0) \
  31                 func(MMC, mmc, 1) \
  32                 func(DHCP, dhcp, na)
  33
  34 #include <config_distro_bootcmd.h>
  35
  36 /* Initial environment variables */
  37 #define CONFIG_EXTRA_ENV_SETTINGS               \
  38         BOOTENV \
  39         "scriptaddr=0x43500000\0" \
  40         "kernel_addr_r=0x40880000\0" \
  41         "image=Image\0" \
  42         "console=ttymxc0,115200\0" \
  43         "fdt_addr=0x43000000\0"                 \
  44         "boot_fdt=try\0" \
  45         "fdt_file=imx8mq-cm.dtb\0" \
  46         "initrd_addr=0x43800000\0"              \
  47         "bootm_size=0x10000000\0" \
  48         "mmcpart=1\0" \
  49         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
  50
  51 /* Link Definitions */
  52
  53 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  54 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  55
  56
  57 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  58 #define PHYS_SDRAM                      0x40000000
  59 #define PHYS_SDRAM_SIZE                                 0x40000000 /* 1 GB DDR */
  60
  61 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(1)
  62
  63 #define CONFIG_SYS_FSL_USDHC_NUM                2
  64 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  65
  66 #endif