1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2022 Linaro
7 #ifndef __IMX8MP_RSB3720_H
8 #define __IMX8MP_RSB3720_H
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
12 #include <asm/arch/imx-regs.h>
13 #include <config_distro_bootcmd.h>
15 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
17 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
18 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
20 /* GUIDs for capsule updatable firmware images */
21 #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
22 EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \
23 0x3a, 0xa0, 0xb0, 0xe9, 0xf9, 0x65)
25 #define IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID \
26 EFI_GUID(0xb5fb6f08, 0xe142, 0x4db1, 0x97, 0xea, \
27 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
29 #ifdef CONFIG_SPL_BUILD
30 #define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
31 * GD_FLG_FULL_MALLOC_INIT \
36 #if defined(CONFIG_NAND_BOOT)
37 #define CONFIG_SPL_NAND_MXS
44 #if defined(CONFIG_CMD_NET)
45 #define CONFIG_FEC_MXC_PHYADDR 4
47 #define DWC_NET_PHYADDR 4
48 #ifdef CONFIG_DWC_ETH_QOS
49 #define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
52 #define PHY_ANEG_TIMEOUT 20000
56 #if CONFIG_IS_ENABLED(CMD_MMC)
57 # define BOOT_TARGET_MMC(func) \
61 # define BOOT_TARGET_MMC(func)
64 #if CONFIG_IS_ENABLED(CMD_PXE)
65 # define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
67 # define BOOT_TARGET_PXE(func)
70 #if CONFIG_IS_ENABLED(CMD_DHCP)
71 # define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
73 # define BOOT_TARGET_DHCP(func)
76 #define BOOT_TARGET_DEVICES(func) \
77 BOOT_TARGET_MMC(func) \
78 BOOT_TARGET_PXE(func) \
79 BOOT_TARGET_DHCP(func)
81 /* Initial environment variables */
82 #define CONFIG_EXTRA_ENV_SETTINGS \
86 "splashimage=0x50000000\0" \
87 "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
88 "fdt_addr=0x43000000\0" \
89 "fdt_addr_r=0x43000000\0" \
91 "dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
92 "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
93 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
94 "initrd_addr=0x43800000\0" \
95 "bootm_size=0x10000000\0" \
96 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
98 "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
99 "mmcautodetect=yes\0" \
100 "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
101 "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
102 "bootscript=echo Running bootscript from mmc ...; " \
104 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
105 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
106 "kernel_addr_r=0x40480000\0" \
107 "pxefile_addr_r=0x40480000\0" \
108 "ramdisk_addr_r=0x43800000\0" \
109 "mmcboot=echo Booting from mmc ...; " \
111 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
112 "bootm ${loadaddr}; " \
114 "if run loadfdt; then " \
115 "booti ${loadaddr} - ${fdt_addr}; " \
117 "echo WARN: Cannot load the DT; " \
120 "netargs=setenv bootargs ${jh_clk} console=${console} " \
122 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
123 "netboot=echo Booting from net ...; " \
125 "if test ${ip_dyn} = yes; then " \
126 "setenv get_cmd dhcp; " \
128 "setenv get_cmd tftp; " \
130 "${get_cmd} ${loadaddr} ${image}; " \
131 "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
132 "bootm ${loadaddr}; " \
134 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
135 "booti ${loadaddr} - ${fdt_addr}; " \
137 "echo WARN: Cannot load the DT; " \
141 /* Link Definitions */
142 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
143 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
146 /* Totally 6GB or 4G DDR */
147 #define CONFIG_SYS_SDRAM_BASE 0x40000000
148 #define PHYS_SDRAM 0x40000000
149 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
150 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
151 #define PHYS_SDRAM_2 0x100000000
152 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
153 #elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
154 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
155 #define PHYS_SDRAM_2 0xC0000000
156 #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
159 #define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
161 #define CONFIG_SYS_FSL_USDHC_NUM 2
162 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
164 #ifdef CONFIG_FSL_FSPI
165 #define FSL_FSPI_FLASH_SIZE SZ_32M
166 #define FSL_FSPI_FLASH_NUM 1
167 #define FSPI0_BASE_ADDR 0x30bb0000
168 #define FSPI0_AMBA_BASE 0x0
169 #define CONFIG_FSPI_QUAD_SUPPORT
171 #define CONFIG_SYS_FSL_FSPI_AHB
174 #ifdef CONFIG_NAND_MXS
177 #define CONFIG_SYS_MAX_NAND_DEVICE 1
178 #define CONFIG_SYS_NAND_BASE 0x20000000
179 #endif /* CONFIG_NAND_MXS */
181 #endif /* __IMX8MP_RSB3720_H */