include/configs/imx8mp_evk.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #ifndef __IMX8MP_EVK_H
   7 #define __IMX8MP_EVK_H
   8
   9 #include <linux/sizes.h>
  10 #include <linux/stringify.h>
  11 #include <asm/arch/imx-regs.h>
  12
  13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
  14
  15 #define CONFIG_SPL_MAX_SIZE             (152 * 1024)
  16 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  17 #define CONFIG_SYS_UBOOT_BASE   (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  21 #define CONFIG_SPL_STACK                0x960000
  22 #define CONFIG_SPL_BSS_START_ADDR       0x0098FC00
  23 #define CONFIG_SPL_BSS_MAX_SIZE         0x400   /* 1 KB */
  24 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  25 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K /* 512 KB */
  26
  27 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  28
  29 #undef CONFIG_DM_MMC
  30
  31 #define CONFIG_POWER_PCA9450
  32
  33 #endif
  34
  35 #if defined(CONFIG_CMD_NET)
  36 #define CONFIG_FEC_MXC_PHYADDR          1
  37 #define FEC_QUIRK_ENET_MAC
  38
  39 #define DWC_NET_PHYADDR                 1
  40
  41 #define PHY_ANEG_TIMEOUT 20000
  42
  43 #endif
  44
  45 #ifndef CONFIG_SPL_BUILD
  46 #define BOOT_TARGET_DEVICES(func) \
  47        func(MMC, mmc, 1) \
  48        func(MMC, mmc, 2)
  49
  50 #include <config_distro_bootcmd.h>
  51 #endif
  52
  53 /* Initial environment variables */
  54 #define CONFIG_EXTRA_ENV_SETTINGS               \
  55         BOOTENV \
  56         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  57         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  58         "image=Image\0" \
  59         "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
  60         "fdt_addr_r=0x43000000\0"                       \
  61         "boot_fdt=try\0" \
  62         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  63         "initrd_addr=0x43800000\0"              \
  64         "bootm_size=0x10000000\0" \
  65         "mmcpart=1\0" \
  66         "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  67
  68 /* Link Definitions */
  69
  70 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  71 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
  72 #define CONFIG_SYS_INIT_SP_OFFSET \
  73         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  74 #define CONFIG_SYS_INIT_SP_ADDR \
  75         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  76
  77 #define CONFIG_MMCROOT                  "/dev/mmcblk1p2"  /* USDHC2 */
  78
  79 /* Totally 6GB DDR */
  80 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  81 #define PHYS_SDRAM                      0x40000000
  82 #define PHYS_SDRAM_SIZE                 0xC0000000      /* 3 GB */
  83 #define PHYS_SDRAM_2                    0x100000000
  84 #define PHYS_SDRAM_2_SIZE               0xC0000000      /* 3 GB */
  85
  86 #define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
  87
  88 /* Monitor Command Prompt */
  89 #define CONFIG_SYS_CBSIZE               2048
  90 #define CONFIG_SYS_MAXARGS              64
  91 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  92 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
  93                                         sizeof(CONFIG_SYS_PROMPT) + 16)
  94
  95 #define CONFIG_SYS_FSL_USDHC_NUM        2
  96 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
  97
  98 #endif