1 /* SPDX-License-Identifier: GPL-2.0+ */
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
13 #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
15 #define CONFIG_SPL_MAX_SIZE (152 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
17 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
18 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
19 #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
21 #ifdef CONFIG_SPL_BUILD
22 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
23 #define CONFIG_SPL_STACK 0x960000
24 #define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
25 #define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
26 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
27 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
29 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
33 #define CONFIG_POWER_PCA9450
37 #if defined(CONFIG_CMD_NET)
38 #define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
40 #define CONFIG_FEC_XCV_TYPE RGMII
41 #define CONFIG_FEC_MXC_PHYADDR 1
42 #define FEC_QUIRK_ENET_MAC
44 #define DWC_NET_PHYADDR 1
46 #define PHY_ANEG_TIMEOUT 20000
50 #ifndef CONFIG_SPL_BUILD
51 #define BOOT_TARGET_DEVICES(func) \
55 #include <config_distro_bootcmd.h>
58 /* Initial environment variables */
59 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
62 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
64 "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
65 "fdt_addr_r=0x43000000\0" \
67 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
68 "initrd_addr=0x43800000\0" \
69 "bootm_size=0x10000000\0" \
70 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
71 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
73 /* Link Definitions */
75 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
76 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000
77 #define CONFIG_SYS_INIT_SP_OFFSET \
78 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
79 #define CONFIG_SYS_INIT_SP_ADDR \
80 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
82 #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
85 #define CONFIG_SYS_SDRAM_BASE 0x40000000
86 #define PHYS_SDRAM 0x40000000
87 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
88 #define PHYS_SDRAM_2 0x100000000
89 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
91 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
93 /* Monitor Command Prompt */
94 #define CONFIG_SYS_CBSIZE 2048
95 #define CONFIG_SYS_MAXARGS 64
96 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
97 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
98 sizeof(CONFIG_SYS_PROMPT) + 16)
100 #define CONFIG_SYS_FSL_USDHC_NUM 2
101 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
103 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1