1e7c44c42a42feffd793362e3d4a588bc6d768d5
[platform/kernel/u-boot.git] / include / configs / imx8mp_evk.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2019 NXP
4  */
5
6 #ifndef __IMX8MP_EVK_H
7 #define __IMX8MP_EVK_H
8
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
12
13 #define CONFIG_SYS_BOOTM_LEN            (32 * SZ_1M)
14
15 #define CONFIG_SPL_MAX_SIZE             (152 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
17 #define CONFIG_SYS_UBOOT_BASE   (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
18
19 #ifdef CONFIG_SPL_BUILD
20 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
21 #define CONFIG_SPL_STACK                0x960000
22 #define CONFIG_SPL_BSS_START_ADDR       0x0098FC00
23 #define CONFIG_SPL_BSS_MAX_SIZE         0x400   /* 1 KB */
24 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
25 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K /* 512 KB */
26
27 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
28
29 #define CONFIG_POWER_PCA9450
30
31 #endif
32
33 #if defined(CONFIG_CMD_NET)
34 #define CONFIG_FEC_MXC_PHYADDR          1
35
36 #define DWC_NET_PHYADDR                 1
37
38 #define PHY_ANEG_TIMEOUT 20000
39
40 #endif
41
42 #ifndef CONFIG_SPL_BUILD
43 #define BOOT_TARGET_DEVICES(func) \
44        func(MMC, mmc, 1) \
45        func(MMC, mmc, 2)
46
47 #include <config_distro_bootcmd.h>
48 #endif
49
50 /* Initial environment variables */
51 #define CONFIG_EXTRA_ENV_SETTINGS               \
52         BOOTENV \
53         "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
54         "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
55         "image=Image\0" \
56         "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
57         "fdt_addr_r=0x43000000\0"                       \
58         "boot_fdt=try\0" \
59         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
60         "initrd_addr=0x43800000\0"              \
61         "bootm_size=0x10000000\0" \
62         "mmcpart=1\0" \
63         "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
64
65 /* Link Definitions */
66
67 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
68 #define CONFIG_SYS_INIT_RAM_SIZE        0x80000
69 #define CONFIG_SYS_INIT_SP_OFFSET \
70         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
71 #define CONFIG_SYS_INIT_SP_ADDR \
72         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
73
74
75 /* Totally 6GB DDR */
76 #define CONFIG_SYS_SDRAM_BASE           0x40000000
77 #define PHYS_SDRAM                      0x40000000
78 #define PHYS_SDRAM_SIZE                 0xC0000000      /* 3 GB */
79 #define PHYS_SDRAM_2                    0x100000000
80 #define PHYS_SDRAM_2_SIZE               0xC0000000      /* 3 GB */
81
82 #define CONFIG_MXC_UART_BASE            UART_BASE_ADDR(2)
83
84 /* Monitor Command Prompt */
85 #define CONFIG_SYS_CBSIZE               2048
86 #define CONFIG_SYS_MAXARGS              64
87 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
88 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
89                                         sizeof(CONFIG_SYS_PROMPT) + 16)
90
91 #endif