1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021 Gateworks Corporation
6 #ifndef __IMX8MM_VENICE_H
7 #define __IMX8MM_VENICE_H
9 #include <asm/arch/imx-regs.h>
10 #include <linux/sizes.h>
12 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
13 #define CONFIG_SYS_MONITOR_LEN SZ_512K
14 #define CONFIG_SYS_UBOOT_BASE \
15 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
17 #ifdef CONFIG_SPL_BUILD
18 #define CONFIG_SPL_STACK 0x920000
19 #define CONFIG_SPL_BSS_START_ADDR 0x910000
20 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
21 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
22 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
24 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
25 #define CONFIG_MALLOC_F_ADDR 0x930000
26 /* For RAW image gives a error info not panic */
27 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31 #define MEM_LAYOUT_ENV_SETTINGS \
32 "fdt_addr_r=0x44000000\0" \
33 "kernel_addr_r=0x42000000\0" \
34 "ramdisk_addr_r=0x46400000\0" \
35 "scriptaddr=0x46000000\0"
37 /* Link Definitions */
39 /* Enable Distro Boot */
40 #ifndef CONFIG_SPL_BUILD
41 #define BOOT_TARGET_DEVICES(func) \
45 #include <config_distro_bootcmd.h>
46 #undef CONFIG_ISO_PARTITION
51 /* Initial environment variables */
52 #define CONFIG_EXTRA_ENV_SETTINGS \
54 MEM_LAYOUT_ENV_SETTINGS \
56 "bootm_size=0x10000000\0" \
57 "ipaddr=192.168.1.22\0" \
58 "serverip=192.168.1.146\0" \
60 "preboot=gsc wd-disable\0" \
61 "console=ttymxc1,115200\0" \
63 "tftpboot $loadaddr $image && " \
64 "setexpr blkcnt $filesize + 0x1ff && " \
65 "setexpr blkcnt $blkcnt / 0x200 && " \
67 "mmc write $loadaddr 0x42 $blkcnt\0" \
69 "tftpboot $kernel_addr_r $image && " \
70 "booti $kernel_addr_r - $fdtcontroladdr\0" \
72 "tftpboot $loadaddr $image && " \
73 "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
75 "tftpboot $loadaddr $image && " \
76 "gzwrite mmc $dev $loadaddr $filesize\0" \
77 "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
79 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
80 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
81 #define CONFIG_SYS_INIT_SP_OFFSET \
82 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83 #define CONFIG_SYS_INIT_SP_ADDR \
84 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
86 #define CONFIG_SYS_SDRAM_BASE 0x40000000
88 /* SDRAM configuration */
89 #define PHYS_SDRAM 0x40000000
90 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
91 #define CONFIG_SYS_BOOTM_LEN SZ_256M
94 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
96 /* Monitor Command Prompt */
97 #define CONFIG_SYS_CBSIZE SZ_2K
98 #define CONFIG_SYS_MAXARGS 64
99 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
101 sizeof(CONFIG_SYS_PROMPT) + 16)
104 #define CONFIG_SYS_FSL_USDHC_NUM 2
105 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
108 #define CONFIG_ETHPRIME "eth0"
109 #define CONFIG_FEC_XCV_TYPE RGMII
110 #define CONFIG_FEC_MXC_PHYADDR 0
111 #define FEC_QUIRK_ENET_MAC
112 #define IMX_FEC_BASE 0x30BE0000