include/configs/imx8mm_venice.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #ifndef __IMX8MM_VENICE_H
   7 #define __IMX8MM_VENICE_H
   8
   9 #include <asm/arch/imx-regs.h>
  10 #include <linux/sizes.h>
  11
  12 #define CONFIG_SPL_MAX_SIZE             (148 * 1024)
  13 #define CONFIG_SYS_MONITOR_LEN          SZ_512K
  14 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  16 #define CONFIG_SYS_UBOOT_BASE   \
  17         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 #define CONFIG_SPL_STACK                0x920000
  21 #define CONFIG_SPL_BSS_START_ADDR       0x910000
  22 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_8K
  23 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  24 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
  25
  26 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  27 #define CONFIG_MALLOC_F_ADDR            0x930000
  28 /* For RAW image gives a error info not panic */
  29 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  30
  31 #endif
  32
  33 #define MEM_LAYOUT_ENV_SETTINGS \
  34         "fdt_addr_r=0x44000000\0" \
  35         "kernel_addr_r=0x42000000\0" \
  36         "ramdisk_addr_r=0x46400000\0" \
  37         "scriptaddr=0x46000000\0"
  38
  39 /* Link Definitions */
  40
  41 /* Enable Distro Boot */
  42 #ifndef CONFIG_SPL_BUILD
  43 #define BOOT_TARGET_DEVICES(func) \
  44         func(MMC, mmc, 1) \
  45         func(MMC, mmc, 2) \
  46         func(DHCP, dhcp, na)
  47 #include <config_distro_bootcmd.h>
  48 #undef CONFIG_ISO_PARTITION
  49 #else
  50 #define BOOTENV
  51 #endif
  52
  53 /* Initial environment variables */
  54 #define CONFIG_EXTRA_ENV_SETTINGS \
  55         BOOTENV \
  56         MEM_LAYOUT_ENV_SETTINGS \
  57         "script=boot.scr\0" \
  58         "bootm_size=0x10000000\0" \
  59         "ipaddr=192.168.1.22\0" \
  60         "serverip=192.168.1.146\0" \
  61         "dev=2\0" \
  62         "preboot=gsc wd-disable\0" \
  63         "console=ttymxc1,115200\0" \
  64         "update_firmware=" \
  65                 "tftpboot $loadaddr $image && " \
  66                 "setexpr blkcnt $filesize + 0x1ff && " \
  67                 "setexpr blkcnt $blkcnt / 0x200 && " \
  68                 "mmc dev $dev && " \
  69                 "mmc write $loadaddr 0x42 $blkcnt\0" \
  70         "boot_net=" \
  71                 "tftpboot $kernel_addr_r $image && " \
  72                 "booti $kernel_addr_r - $fdtcontroladdr\0" \
  73         "update_rootfs=" \
  74                 "tftpboot $loadaddr $image && " \
  75                 "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
  76         "update_all=" \
  77                 "tftpboot $loadaddr $image && " \
  78                 "gzwrite mmc $dev $loadaddr $filesize\0" \
  79         "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
  80
  81 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  82 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
  83 #define CONFIG_SYS_INIT_SP_OFFSET \
  84         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85 #define CONFIG_SYS_INIT_SP_ADDR \
  86         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  87
  88 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  89
  90 /* SDRAM configuration */
  91 #define PHYS_SDRAM                      0x40000000
  92 #define PHYS_SDRAM_SIZE                 SZ_1G /* 1GB DDR */
  93 #define CONFIG_SYS_BOOTM_LEN            SZ_256M
  94
  95 /* UART */
  96 #define CONFIG_MXC_UART_BASE            UART2_BASE_ADDR
  97
  98 /* Monitor Command Prompt */
  99 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 100 #define CONFIG_SYS_CBSIZE               SZ_2K
 101 #define CONFIG_SYS_MAXARGS              64
 102 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 103 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 104                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 105
 106 /* USDHC */
 107 #define CONFIG_SYS_FSL_USDHC_NUM        2
 108 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 109 #define CONFIG_SYS_MMC_IMG_LOAD_PART    1
 110
 111 /* FEC */
 112 #define CONFIG_ETHPRIME                 "eth0"
 113 #define CONFIG_FEC_XCV_TYPE             RGMII
 114 #define CONFIG_FEC_MXC_PHYADDR          0
 115 #define FEC_QUIRK_ENET_MAC
 116 #define IMX_FEC_BASE                    0x30BE0000
 117
 118 #endif