1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2020 Engicam srl
4 * Copyright (c) 2020 Amarula Solutions(India)
7 #ifndef __IMX8MM_ICORE_MX8MM_H
8 #define __IMX8MM_ICORE_MX8MM_H
10 #include <linux/sizes.h>
11 #include <asm/arch/imx-regs.h>
13 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
14 #define CONFIG_SYS_MONITOR_LEN SZ_512K
15 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
16 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
17 #define CONFIG_SYS_UBOOT_BASE \
18 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
20 #ifdef CONFIG_SPL_BUILD
21 # define CONFIG_SPL_STACK 0x920000
22 # define CONFIG_SPL_BSS_START_ADDR 0x910000
23 # define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
24 # define CONFIG_SYS_SPL_MALLOC_START 0x42200000
25 # define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
27 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
28 # define CONFIG_MALLOC_F_ADDR 0x930000
29 /* For RAW image gives a error info not panic */
30 # define CONFIG_SPL_ABORT_ON_RAW_IMAGE
31 #endif /* CONFIG_SPL_BUILD */
33 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
34 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
36 #ifndef CONFIG_SPL_BUILD
37 #define BOOT_TARGET_DEVICES(func) \
40 #include <config_distro_bootcmd.h>
41 #undef CONFIG_ISO_PARTITION
46 #define ENV_MEM_LAYOUT_SETTINGS \
47 "fdt_addr_r=0x44000000\0" \
48 "kernel_addr_r=0x42000000\0" \
49 "ramdisk_addr_r=0x46400000\0" \
50 "scriptaddr=0x46000000\0"
52 #define CONFIG_EXTRA_ENV_SETTINGS \
53 ENV_MEM_LAYOUT_SETTINGS \
54 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
55 "console=ttymxc1,115200\0" \
58 /* Link Definitions */
59 #define CONFIG_SYS_LOAD_ADDR 0x40480000
61 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
62 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
63 #define CONFIG_SYS_INIT_SP_OFFSET \
64 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
65 #define CONFIG_SYS_INIT_SP_ADDR \
66 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
68 /* Size of malloc() pool */
69 #define CONFIG_SYS_MALLOC_LEN SZ_32M
70 #define CONFIG_SYS_SDRAM_BASE 0x40000000
72 /* SDRAM configuration */
73 #define PHYS_SDRAM 0x40000000
74 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
75 #define CONFIG_SYS_BOOTM_LEN SZ_256M
77 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
78 #define CONFIG_SYS_MEMTEST_END \
79 (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
82 #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
84 /* Monitor Command Prompt */
85 #define CONFIG_SYS_CBSIZE 2048
86 #define CONFIG_SYS_MAXARGS 64
87 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
88 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
89 sizeof(CONFIG_SYS_PROMPT) + 16)
92 #define CONFIG_SYS_FSL_USDHC_NUM 2
93 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
94 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
96 #endif /* __IMX8MM_ICORE_MX8MM_H */