1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2022 Marek Vasut <marex@denx.de>
6 #ifndef __IMX8MM_DATA_MODUL_EDM_SBC_H
7 #define __IMX8MM_DATA_MODUL_EDM_SBC_H
9 #include <linux/sizes.h>
10 #include <linux/stringify.h>
11 #include <asm/arch/imx-regs.h>
13 #define CONFIG_SYS_BOOTM_LEN SZ_128M
15 #define CONFIG_SPL_MAX_SIZE (148 * 1024)
16 #define CONFIG_SYS_MONITOR_LEN SZ_1M
18 #define CONFIG_SPL_STACK 0x920000
19 #ifdef CONFIG_SPL_BUILD
20 #define CONFIG_SPL_BSS_START_ADDR 0x910000
21 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 kiB */
22 #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
23 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M /* 16 MiB */
25 #define CONFIG_MALLOC_F_ADDR 0x930000
27 /* For RAW image gives a error info not panic */
28 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
32 /* Link Definitions */
33 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
34 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000
35 #define CONFIG_SYS_INIT_SP_OFFSET \
36 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
37 #define CONFIG_SYS_INIT_SP_ADDR \
38 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
40 #define CONFIG_SYS_SDRAM_BASE 0x40000000
41 #define PHYS_SDRAM 0x40000000
42 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */
44 /* Monitor Command Prompt */
45 #define CONFIG_SYS_CBSIZE 2048
46 #define CONFIG_SYS_MAXARGS 64
47 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
48 #define CONFIG_SYS_PBSIZE \
49 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
51 /* PHY needs a longer autonegotiation timeout after reset */
52 #define PHY_ANEG_TIMEOUT 20000
55 #define CONFIG_SYS_FSL_USDHC_NUM 2
56 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
58 #if !defined(CONFIG_SPL_BUILD)
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \
65 /* Give slow devices beyond USB HUB chance to come up. */ \
66 "usb_pgood_delay=2000\0" \
68 /* RAM block at DRAM offset 256..768 MiB */ \
69 "ram ram0=ram ram 0x50000000 0x20000000&" \
70 /* 16 MiB SPI NOR */ \
71 "mtd nor0=sf raw 0x0 0x1000000\0" \
73 "sf probe ; " /* Scan for SPI NOR, needed by DFU */ \
74 "run dmo_usb_start_hub ; " \
75 /* Attempt to start USB and Network console */ \
76 "run dmo_usb_cdc_acm_start ; " \
77 "run dmo_netconsole_start\0" \
79 "setenv dmo_update_env true ; saveenv ; saveenv\0" \
80 "dmo_usb_cdc_acm_start=" \
81 "if test \"${dmo_usb_cdc_acm_enabled}\" = \"true\" ; then "\
82 /* Ungate IMX8MM_CLK_USB1_CTRL_ROOT */ \
83 "mw 0x303844d0 3 ; " \
84 /* Read USBNC_n_PHY_STATUS BIT(4) VBUS_VLD */ \
85 "setexpr.l usbnc_n_phy_status *0x32e4023c \\\\& 0x8 ; " \
86 /* If USB OTG has valid VBUS, enable CDC ACM */ \
87 "if test \"${usbnc_n_phy_status}\" -eq 8 ; then "\
89 "setenv stderr ${stderr},usbacm && " \
90 "setenv stdout ${stdout},usbacm && " \
91 "setenv stdin ${stdin},usbacm ; " \
94 "dmo_usb_start_hub=" \
96 /* Reset the USB USB */ \
97 "gpio clear GPIO5_2 ; sleep 0.01 ; " /* t1 > 1us */ \
98 "gpio set GPIO5_2 ; sleep 0.01 ; " /* t5 > 3us */ \
99 /* Write chunks of descriptor into the USB HUB */ \
100 "mw.l 0x7e1000 0x14042417 ; mw.l 0x7e1004 0x9b0bb325 ; "\
101 "mw.l 0x7e1008 0x00000220 ; mw.l 0x7e100c 0x01320100 ; "\
102 "mw.l 0x7e1010 0x00003232 ; mw.l 0x7e1014 0x4d000909 ; "\
103 "i2c write 0x7e1000 0x2c 0x00 0x18 -s ; " \
104 "mw.l 0x7e1000 0x6300690f ; mw.l 0x7e1004 0x6f007200 ; "\
105 "mw.l 0x7e1008 0x68006300 ; mw.l 0x7e100c 0x70006900 ; "\
106 "i2c write 0x7e1000 0x2c 0x18 0x10 -s ; " \
107 "mw.l 0x7e1000 0x53005511 ; mw.l 0x7e1004 0x32004200 ; "\
108 "mw.l 0x7e1008 0x31003500 ; mw.l 0x7e100c 0x42003400 ; "\
109 "mw.l 0x7e1010 0x00006900 ; " \
110 "i2c write 0x7e1000 0x2c 0x54 0x12 -s ; " \
111 "mw.l 0x7e1000 0x00000101 ; " \
112 "i2c write 0x7e1000 0x2c 0xff 0x2 -s\0" \
113 "dmo_netconsole_start=" \
114 "if test \"${dmo_netconsole_enabled}\" = \"true\" ; then "\
115 "setenv autoload false && " \
117 "setenv autoload && " \
118 "setenv ncip ${serverip} && " \
119 "setenv stderr ${stderr},nc && " \
120 "setenv stdout ${stdout},nc && " \
121 "setenv stdin ${stdin},nc ; " \