Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
[platform/kernel/u-boot.git] / include / configs / imx27lite.h
1 /*
2  * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17  * MA 02111-1307 USA
18  */
19
20 #ifndef __CONFIG_H
21 #define __CONFIG_H
22
23 /*
24  * SoC Configuration
25  */
26 #define CONFIG_ARM926EJS                        /* arm926ejs CPU core */
27 #define CONFIG_MX27
28 #define CONFIG_IMX27LITE
29 #define CONFIG_MX27_CLK32       32768           /* OSC32K frequency */
30 #define CONFIG_SYS_HZ           1000
31
32 #define CONFIG_DISPLAY_CPUINFO
33
34 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
35 #define CONFIG_SETUP_MEMORY_TAGS        1
36 #define CONFIG_INITRD_TAG               1
37
38 /*
39  * Lowlevel configuration
40  */
41 #define SDRAM_ESDCFG_REGISTER_VAL(cas)  \
42                 (ESDCFG_TRC(10) |       \
43                 ESDCFG_TRCD(3) |        \
44                 ESDCFG_TCAS(cas) |      \
45                 ESDCFG_TRRD(1) |        \
46                 ESDCFG_TRAS(5) |        \
47                 ESDCFG_TWR |            \
48                 ESDCFG_TMRD(2) |        \
49                 ESDCFG_TRP(2) |         \
50                 ESDCFG_TXP(3))
51
52 #define SDRAM_ESDCTL_REGISTER_VAL       \
53                 (ESDCTL_PRCT(0) |       \
54                  ESDCTL_BL |            \
55                  ESDCTL_PWDT(0) |       \
56                  ESDCTL_SREFR(3) |      \
57                  ESDCTL_DSIZ_32 |       \
58                  ESDCTL_COL10 |         \
59                  ESDCTL_ROW13 |         \
60                  ESDCTL_SDE)
61
62 #define SDRAM_ALL_VAL           0xf00
63
64 #define SDRAM_MODE_REGISTER_VAL 0x33    /* BL: 8, CAS: 3 */
65 #define SDRAM_EXT_MODE_REGISTER_VAL     0x1000000
66
67 #define MPCTL0_VAL      0x1ef15d5
68
69 #define SPCTL0_VAL      0x043a1c09
70
71 #define CSCR_VAL        0x33f08107
72
73 #define PCDR0_VAL       0x120470c3
74 #define PCDR1_VAL       0x03030303
75 #define PCCR0_VAL       0xffffffff
76 #define PCCR1_VAL       0xfffffffc
77
78 #define AIPI1_PSR0_VAL  0x20040304
79 #define AIPI1_PSR1_VAL  0xdffbfcfb
80 #define AIPI2_PSR0_VAL  0x07ffc200
81 #define AIPI2_PSR1_VAL  0xffffffff
82
83 /*
84  * Memory Info
85  */
86 /* malloc() len */
87 #define CONFIG_SYS_MALLOC_LEN           (0x10000 + 512 * 1024)
88 /* reserved for initial data */
89 #define CONFIG_SYS_GBL_DATA_SIZE        128
90 /* memtest start address */
91 #define CONFIG_SYS_MEMTEST_START        0xA0000000
92 #define CONFIG_SYS_MEMTEST_END          0xA1000000      /* 16MB RAM test */
93 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
94 #define CONFIG_STACKSIZE        (256 * 1024)    /* regular stack */
95 #define PHYS_SDRAM_1            0xA0000000      /* DDR Start */
96 #define PHYS_SDRAM_1_SIZE       0x08000000      /* DDR size 128MB */
97
98 /*
99  * Serial Driver info
100  */
101 #define CONFIG_MXC_UART
102 #define CONFIG_SYS_MX27_UART1
103 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
104 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
105 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
106
107 /*
108  * Flash & Environment
109  */
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_FLASH_CFI_DRIVER
112 #define CONFIG_SYS_FLASH_CFI
113 /* Use buffered writes (~10x faster) */
114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
115 /* Use hardware sector protection */
116 #define CONFIG_SYS_FLASH_PROTECTION             1
117 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of flash banks */
118 #define CONFIG_SYS_FLASH_SECT_SZ        0x2000  /* 8KB sect size Intel Flash */
119 /* end of flash */
120 #define CONFIG_ENV_OFFSET               (PHYS_FLASH_SIZE - 0x20000)
121 /* CS2 Base address */
122 #define PHYS_FLASH_1                    0xc0000000
123 /* Flash Base for U-Boot */
124 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
125 /* Flash size 2MB */
126 #define PHYS_FLASH_SIZE                 0x200000
127 #define CONFIG_SYS_MAX_FLASH_SECT       (PHYS_FLASH_SIZE / \
128                 CONFIG_SYS_FLASH_SECT_SZ)
129 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
130 #define CONFIG_SYS_MONITOR_LEN          0x40000         /* Reserve 256KiB */
131 #define CONFIG_ENV_SECT_SIZE            0x10000         /* Env sector Size */
132 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
133 /* Address and size of Redundant Environment Sector     */
134 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
135 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
136
137 /*
138  * Ethernet
139  */
140 #define CONFIG_FEC_MXC
141 #define CONFIG_FEC_MXC_PHYADDR          0x1f
142 #define CONFIG_MII
143 #define CONFIG_NET_MULTI
144
145 /*
146  * MTD
147  */
148 #define CONFIG_MTD_DEVICE
149
150 /*
151  * NAND
152  */
153 #define CONFIG_NAND_MXC
154 #define CONFIG_MXC_NAND_REGS_BASE       0xd8000000
155 #define CONFIG_SYS_MAX_NAND_DEVICE      1
156 #define CONFIG_SYS_NAND_BASE            0xd8000000
157 #define CONFIG_JFFS2_NAND
158 #define CONFIG_MXC_NAND_HWECC
159
160 /*
161  * SD/MMC
162  */
163 #define CONFIG_MMC
164 #define CONFIG_GENERIC_MMC
165 #define CONFIG_MXC_MMC
166 #define CONFIG_MXC_MCI_REGS_BASE        0x10014000
167 #define CONFIG_DOS_PARTITION
168
169 /*
170  * MTD partitions
171  */
172 #define CONFIG_CMD_MTDPARTS
173 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=mxc_nand.0"
174 #define MTDPARTS_DEFAULT                        \
175         "mtdparts="                             \
176                 "physmap-flash.0:"              \
177                         "256k(U-Boot),"         \
178                         "1664k(user),"          \
179                         "64k(env1),"            \
180                         "64k(env2);"            \
181                 "mxc_nand.0:"                   \
182                         "128k(IPL-SPL),"        \
183                         "4m(kernel),"           \
184                         "22m(rootfs),"          \
185                         "-(userfs)"
186
187 /*
188  * U-Boot general configuration
189  */
190 #define CONFIG_BOOTFILE         "uImage"        /* Boot file name */
191 #define CONFIG_SYS_PROMPT       "=> "   /* Monitor Command Prompt */
192 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size  */
193 /* Print buffer sz */
194 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
195                 sizeof(CONFIG_SYS_PROMPT) + 16)
196 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
197 /* Boot Argument Buffer Size */
198 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
199 #define CONFIG_CMDLINE_EDITING
200 #define CONFIG_SYS_LONGHELP
201
202 /*
203  * U-Boot commands
204  */
205 #include <config_cmd_default.h>
206 #define CONFIG_CMD_ASKENV
207 #define CONFIG_CMD_DHCP
208 #define CONFIG_CMD_DIAG
209 #define CONFIG_CMD_FAT
210 #define CONFIG_CMD_JFFS2
211 #define CONFIG_CMD_MII
212 #define CONFIG_CMD_MMC
213 #define CONFIG_CMD_NAND
214 #define CONFIG_CMD_PING
215
216 #define CONFIG_BOOTDELAY        5
217
218 #define CONFIG_LOADADDR         0xa0800000      /* loadaddr env var */
219 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
220
221 #define xstr(s) str(s)
222 #define str(s)  #s
223
224 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
225         "netdev=eth0\0"                                                 \
226         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
227                 "nfsroot=${serverip}:${rootpath}\0"                     \
228         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
229         "addip=setenv bootargs ${bootargs} "                            \
230                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
231                 ":${hostname}:${netdev}:off panic=1\0"                  \
232         "addtty=setenv bootargs ${bootargs}"                            \
233                 " console=ttymxc0,${baudrate}\0"                        \
234         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
235         "addmisc=setenv bootargs ${bootargs}\0"                         \
236         "u-boot=imx27/u-boot.bin\0"                                     \
237         "kernel_addr_r=a0800000\0"                                      \
238         "hostname=imx27\0"                                              \
239         "bootfile=imx27/uImage\0"                                       \
240         "rootpath=/opt/eldk-4.2-arm/arm\0"                              \
241         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
242                 "run nfsargs addip addtty addmtd addmisc;"              \
243                 "bootm\0"                                               \
244         "bootcmd=run net_nfs\0"                                 \
245         "load=tftp ${loadaddr} ${u-boot}\0"                             \
246         "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)             \
247                 " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)      \
248                 " +${filesize};cp.b ${fileaddr} "                       \
249                 xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"          \
250         "upd=run load update\0"                                         \
251
252 #endif /* __CONFIG_H */