Merge branch 'master' of git://git.denx.de/u-boot
[platform/kernel/u-boot.git] / include / configs / ids8313.h
1 /*
2  * (C) Copyright 2013
3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  *
5  * Based on:
6  * Copyright (c) 2011 IDS GmbH, Germany
7  * Sergej Stepanov <ste@ids.de>
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_MPC831x
19 #define CONFIG_MPC8313
20 #define CONFIG_IDS8313
21
22
23 #define CONFIG_FSL_ELBC
24
25 #define CONFIG_MISC_INIT_R
26
27 #define CONFIG_BOOT_RETRY_TIME          900
28 #define CONFIG_BOOT_RETRY_MIN           30
29 #define CONFIG_BOOTDELAY                1
30 #define CONFIG_RESET_TO_RETRY
31
32 #define CONFIG_83XX_CLKIN               66000000        /* in Hz */
33 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
34
35 #define CONFIG_SYS_IMMR         0xF0000000
36
37 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
38 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
39
40 /*
41  * Hardware Reset Configuration Word
42  * if CLKIN is 66.000MHz, then
43  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
44  */
45 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
46                              HRCWL_DDR_TO_SCB_CLK_2X1 |\
47                              HRCWL_CSB_TO_CLKIN_2X1 |\
48                              HRCWL_CORE_TO_CSB_2X1)
49
50 #define CONFIG_SYS_HRCW_HIGH    (HRCWH_PCI_HOST |\
51                                  HRCWH_CORE_ENABLE |\
52                                  HRCWH_FROM_0XFFF00100 |\
53                                  HRCWH_BOOTSEQ_DISABLE |\
54                                  HRCWH_SW_WATCHDOG_DISABLE |\
55                                  HRCWH_ROM_LOC_LOCAL_8BIT |\
56                                  HRCWH_RL_EXT_LEGACY |\
57                                  HRCWH_TSEC1M_IN_MII |\
58                                  HRCWH_TSEC2M_IN_MII |\
59                                  HRCWH_BIG_ENDIAN)
60
61 #define CONFIG_SYS_SICRH        0x00000000
62 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
63
64 #define CONFIG_HWCONFIG
65
66 #define CONFIG_SYS_HID0_INIT    0x000000000
67 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
68                                  HID0_ENABLE_INSTRUCTION_CACHE |\
69                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
70
71 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
72
73 /*
74  * Definitions for initial stack pointer and data area (in DCACHE )
75  */
76 #define CONFIG_SYS_INIT_RAM_LOCK
77 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
78 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
79 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
80 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
81                                          - CONFIG_SYS_GBL_DATA_SIZE)
82 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
83
84 /*
85  * Local Bus LCRR and LBCR regs
86  */
87 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
88 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
89 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
90                                          (0xFF << LBCR_BMT_SHIFT) |\
91                                          0xF)
92
93 #define CONFIG_SYS_LBC_MRTPR            0x20000000
94
95 /*
96  * Internal Definitions
97  */
98 /*
99  * DDR Setup
100  */
101 #define CONFIG_SYS_DDR_BASE             0x00000000
102 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
104
105 /*
106  * Manually set up DDR parameters,
107  * as this board has not the SPD connected to I2C.
108  */
109 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
110 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
111                                          0x00010000 |\
112                                          CSCONFIG_ROW_BIT_13 |\
113                                          CSCONFIG_COL_BIT_10)
114
115 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
116                                          CSCONFIG_BANK_BIT_3)
117
118 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
119 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
120                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
121                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
122                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
123                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
124                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
125                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
126                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
127 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
128                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
129                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
130                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
131                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
132                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
133                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
134                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
135 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
136                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
137                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
138                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
139                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
140                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
141                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
142
143 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
144                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
145
146 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
147                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
148                                          SDRAM_CFG_DBW_32 |\
149                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
150
151 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
152 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
153                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
154 #define CONFIG_SYS_DDR_MODE_2           0x00000000
155 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
156 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
157                                          DDRCDR_PZ_NOMZ |\
158                                          DDRCDR_NZ_NOMZ |\
159                                          DDRCDR_ODT |\
160                                          DDRCDR_M_ODR |\
161                                          DDRCDR_Q_DRN)
162
163 /*
164  * on-board devices
165  */
166 #define CONFIG_TSEC1
167 #define CONFIG_TSEC2
168 #define CONFIG_TSEC_ENET
169 #define CONFIG_HARD_SPI
170 #define CONFIG_HARD_I2C
171
172 /*
173  * NOR FLASH setup
174  */
175 #define CONFIG_SYS_FLASH_CFI
176 #define CONFIG_FLASH_CFI_DRIVER
177 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
178 #define CONFIG_FLASH_SHOW_PROGRESS      50
179 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
180
181 #define CONFIG_SYS_FLASH_BASE           0xFF800000
182 #define CONFIG_SYS_FLASH_SIZE           8
183 #define CONFIG_SYS_FLASH_PROTECTION
184
185 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
186 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016
187
188 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |\
189                                          BR_PS_8 |\
190                                          BR_MS_GPCM |\
191                                          BR_V)
192
193 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
194                                          OR_GPCM_SCY_10 |\
195                                          OR_GPCM_EHTR |\
196                                          OR_GPCM_TRLX |\
197                                          OR_GPCM_CSNT |\
198                                          OR_GPCM_EAD)
199 #define CONFIG_SYS_MAX_FLASH_BANKS      1
200 #define CONFIG_SYS_MAX_FLASH_SECT       128
201
202 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
203 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
204
205 /*
206  * NAND FLASH setup
207  */
208 #define CONFIG_SYS_NAND_BASE            0xE1000000
209 #define CONFIG_SYS_MAX_NAND_DEVICE      1
210 #define CONFIG_SYS_NAND_MAX_CHIPS       1
211 #define CONFIG_NAND_FSL_ELBC
212 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
213 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
214 #define NAND_CACHE_PAGES                64
215
216 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
217 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
218 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
219 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR1_PRELIM
220
221 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_NAND_BASE) |\
222                                  (2<<BR_DECC_SHIFT) |\
223                                  BR_PS_8 |\
224                                  BR_MS_FCM |\
225                                  BR_V)
226
227 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000 |\
228                                  OR_FCM_PGS |\
229                                  OR_FCM_CSCT |\
230                                  OR_FCM_CST |\
231                                  OR_FCM_CHT |\
232                                  OR_FCM_SCY_4 |\
233                                  OR_FCM_TRLX |\
234                                  OR_FCM_EHTR |\
235                                  OR_FCM_RST)
236
237 /*
238  * MRAM setup
239  */
240 #define CONFIG_SYS_MRAM_BASE            0xE2000000
241 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
242 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_MRAM_BASE
243 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* 128 Kb  */
244
245 #define CONFIG_SYS_OR_TIMING_MRAM
246
247 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_MRAM_BASE |\
248                                          BR_PS_8 |\
249                                          BR_MS_GPCM |\
250                                          BR_V)
251
252 #define CONFIG_SYS_OR2_PRELIM           0xFFFE0C74
253
254 /*
255  * CPLD setup
256  */
257 #define CONFIG_SYS_CPLD_BASE            0xE3000000
258 #define CONFIG_SYS_CPLD_SIZE            0x8000
259 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CPLD_BASE
260 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E
261
262 #define CONFIG_SYS_OR_TIMING_MRAM
263
264 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_CPLD_BASE |\
265                                          BR_PS_8 |\
266                                          BR_MS_GPCM |\
267                                          BR_V)
268
269 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8814
270
271 /*
272  * HW-Watchdog
273  */
274 #define CONFIG_WATCHDOG         1
275 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
276
277 /*
278  * I2C setup
279  */
280 #define CONFIG_CMD_I2C
281 #define CONFIG_SYS_I2C
282 #define CONFIG_SYS_I2C_FSL
283 #define CONFIG_SYS_FSL_I2C_SPEED        400000
284 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
285 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
286 #define CONFIG_RTC_PCF8563
287 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
288
289 /*
290  * SPI setup
291  */
292 #ifdef CONFIG_HARD_SPI
293 #define CONFIG_MPC8XXX_SPI
294 #define CONFIG_CMD_SPI
295 #define CONFIG_SYS_GPIO1_PRELIM
296 #define CONFIG_SYS_GPIO1_DIR            0x00000001
297 #define CONFIG_SYS_GPIO1_DAT            0x00000001
298 #endif
299
300 /*
301  * Ethernet setup
302  */
303 #ifdef CONFIG_TSEC1
304 #define CONFIG_HAS_ETH0
305 #define CONFIG_TSEC1_NAME               "TSEC0"
306 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
307 #define TSEC1_PHY_ADDR                  0x1
308 #define TSEC1_FLAGS                     TSEC_GIGABIT
309 #define TSEC1_PHYIDX                    0
310 #endif
311
312 #ifdef CONFIG_TSEC2
313 #define CONFIG_HAS_ETH1
314 #define CONFIG_TSEC2_NAME               "TSEC1"
315 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
316 #define TSEC2_PHY_ADDR                  0x3
317 #define TSEC2_FLAGS                     TSEC_GIGABIT
318 #define TSEC2_PHYIDX                    0
319 #endif
320 #define CONFIG_ETHPRIME         "TSEC1"
321
322 /*
323  * Serial Port
324  */
325 #define CONFIG_CONS_INDEX               1
326 #define CONFIG_SYS_NS16550
327 #define CONFIG_SYS_NS16550_SERIAL
328 #define CONFIG_SYS_NS16550_REG_SIZE     1
329
330 #define CONFIG_SYS_BAUDRATE_TABLE       \
331         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
334 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
335
336 #define CONFIG_HAS_FSL_DR_USB
337 #define CONFIG_SYS_SCCR_USBDRCM 3
338
339 /*
340  * BAT's
341  */
342 #define CONFIG_HIGH_BATS
343
344 /* DDR @ 0x00000000 */
345 #define CONFIG_SYS_IBAT0L               (CONFIG_SYS_SDRAM_BASE |\
346                                          BATL_PP_10)
347 #define CONFIG_SYS_IBAT0U               (CONFIG_SYS_SDRAM_BASE |\
348                                          BATU_BL_256M |\
349                                          BATU_VS |\
350                                          BATU_VP)
351 #define CONFIG_SYS_DBAT0L               CONFIG_SYS_IBAT0L
352 #define CONFIG_SYS_DBAT0U               CONFIG_SYS_IBAT0U
353
354 /* Initial RAM @ 0xFD000000 */
355 #define CONFIG_SYS_IBAT1L               (CONFIG_SYS_INIT_RAM_ADDR |\
356                                          BATL_PP_10 |\
357                                          BATL_GUARDEDSTORAGE)
358 #define CONFIG_SYS_IBAT1U               (CONFIG_SYS_INIT_RAM_ADDR |\
359                                          BATU_BL_256K |\
360                                          BATU_VS |\
361                                          BATU_VP)
362 #define CONFIG_SYS_DBAT1L               CONFIG_SYS_IBAT1L
363 #define CONFIG_SYS_DBAT1U               CONFIG_SYS_IBAT1U
364
365 /* FLASH @ 0xFF800000 */
366 #define CONFIG_SYS_IBAT2L               (CONFIG_SYS_FLASH_BASE |\
367                                          BATL_PP_10 |\
368                                          BATL_GUARDEDSTORAGE)
369 #define CONFIG_SYS_IBAT2U               (CONFIG_SYS_FLASH_BASE |\
370                                          BATU_BL_8M |\
371                                          BATU_VS |\
372                                          BATU_VP)
373 #define CONFIG_SYS_DBAT2L               (CONFIG_SYS_FLASH_BASE |\
374                                          BATL_PP_10 |\
375                                          BATL_CACHEINHIBIT |\
376                                          BATL_GUARDEDSTORAGE)
377 #define CONFIG_SYS_DBAT2U               CONFIG_SYS_IBAT2U
378
379 #define CONFIG_SYS_IBAT3L               (0)
380 #define CONFIG_SYS_IBAT3U               (0)
381 #define CONFIG_SYS_DBAT3L               CONFIG_SYS_IBAT3L
382 #define CONFIG_SYS_DBAT3U               CONFIG_SYS_IBAT3U
383
384 #define CONFIG_SYS_IBAT4L               (0)
385 #define CONFIG_SYS_IBAT4U               (0)
386 #define CONFIG_SYS_DBAT4L               CONFIG_SYS_IBAT4L
387 #define CONFIG_SYS_DBAT4U               CONFIG_SYS_IBAT4U
388
389 /* IMMRBAR @ 0xF0000000 */
390 #define CONFIG_SYS_IBAT5L               (CONFIG_SYS_IMMR |\
391                                          BATL_PP_10 |\
392                                          BATL_CACHEINHIBIT |\
393                                          BATL_GUARDEDSTORAGE)
394 #define CONFIG_SYS_IBAT5U               (CONFIG_SYS_IMMR |\
395                                          BATU_BL_128M |\
396                                          BATU_VS |\
397                                          BATU_VP)
398 #define CONFIG_SYS_DBAT5L               CONFIG_SYS_IBAT5L
399 #define CONFIG_SYS_DBAT5U               CONFIG_SYS_IBAT5U
400
401 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
402 #define CONFIG_SYS_IBAT6L               (0xE0000000 |\
403                                          BATL_PP_10 |\
404                                          BATL_GUARDEDSTORAGE)
405 #define CONFIG_SYS_IBAT6U               (0xE0000000 |\
406                                          BATU_BL_256M |\
407                                          BATU_VS |\
408                                          BATU_VP)
409 #define CONFIG_SYS_DBAT6L               CONFIG_SYS_IBAT6L
410 #define CONFIG_SYS_DBAT6U               CONFIG_SYS_IBAT6U
411
412 #define CONFIG_SYS_IBAT7L               (0)
413 #define CONFIG_SYS_IBAT7U               (0)
414 #define CONFIG_SYS_DBAT7L               CONFIG_SYS_IBAT7L
415 #define CONFIG_SYS_DBAT7U               CONFIG_SYS_IBAT7U
416
417 /*
418  * U-Boot environment setup
419  */
420 #define CONFIG_CMD_DHCP
421 #define CONFIG_CMD_PING
422 #define CONFIG_CMD_NAND
423 #define CONFIG_CMD_SNTP
424 #define CONFIG_CMD_MII
425 #define CONFIG_CMD_DATE
426 #define CONFIG_CMDLINE_EDITING
427 #define CONFIG_CMD_JFFS2
428 #define CONFIG_BOOTP_SUBNETMASK
429 #define CONFIG_BOOTP_GATEWAY
430 #define CONFIG_BOOTP_HOSTNAME
431 #define CONFIG_BOOTP_BOOTPATH
432 #define CONFIG_BOOTP_BOOTFILESIZE
433 /* pass open firmware flat tree */
434 #define CONFIG_OF_LIBFDT
435 #define CONFIG_OF_BOARD_SETUP
436 #define CONFIG_OF_STDOUT_VIA_ALIAS
437
438 /*
439  * The reserved memory
440  */
441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
442 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
443 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
444
445 /*
446  * Environment Configuration
447  */
448 #define CONFIG_ENV_IS_IN_FLASH
449 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
450                                 + CONFIG_SYS_MONITOR_LEN)
451 #define CONFIG_ENV_SIZE         0x20000
452 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
453 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
454
455
456 #define CONFIG_NETDEV                   eth1
457 #define CONFIG_HOSTNAME         ids8313
458 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
459 #define CONFIG_BOOTFILE         "ids8313/uImage"
460 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
461 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
462 #define CONFIG_LOADADDR         0x400000
463 #define CONFIG_CMD_ENV_FLAGS
464 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
465
466 #define CONFIG_BAUDRATE         115200
467
468 /* Initial Memory map for Linux*/
469 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
470
471 /*
472  * Miscellaneous configurable options
473  */
474 #define CONFIG_SYS_LONGHELP
475 #define CONFIG_SYS_CBSIZE               1024
476 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE \
477                                          + sizeof(CONFIG_SYS_PROMPT)+16)
478 #define CONFIG_SYS_MAXARGS              16
479 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
480 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser    */
481 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
482
483 #define CONFIG_SYS_MEMTEST_START        0x00001000
484 #define CONFIG_SYS_MEMTEST_END          0x00C00000
485
486 #define CONFIG_SYS_LOAD_ADDR            0x100000
487 #define CONFIG_MII
488 #define CONFIG_LOADS_ECHO
489 #define CONFIG_TIMESTAMP
490 #define CONFIG_PREBOOT                  "echo;" \
491                                         "echo Type \\\"run nfsboot\\\" " \
492                                         "to mount root filesystem over NFS;echo"
493 #undef  CONFIG_BOOTARGS
494 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
495 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
496
497 #define CONFIG_JFFS2_NAND
498 #define CONFIG_JFFS2_DEV                "0"
499
500 /* mtdparts command line support */
501 #define CONFIG_CMD_MTDPARTS
502 #define CONFIG_FLASH_CFI_MTD
503 #define CONFIG_MTD_DEVICE
504 #define MTDIDS_DEFAULT          "nor0=ff800000.flash,nand0=e1000000.flash"
505 #define MTDPARTS_DEFAULT        "mtdparts=ff800000.flash:7m(dum)," \
506                                         "768k(BOOT-BIN)," \
507                                         "128k(BOOT-ENV),128k(BOOT-REDENV);" \
508                                         "e1000000.flash:-(ubi)"
509
510 #define CONFIG_EXTRA_ENV_SETTINGS \
511         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
512         "ethprime=TSEC1\0"                                              \
513         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
514         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
515                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
516                 " +${filesize}; "                                       \
517                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
518                 " +${filesize}; "                                       \
519                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
520                 " ${filesize}; "                                        \
521                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
522                 " +${filesize}; "                                       \
523                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
524                 " ${filesize}\0"                                        \
525         "console=ttyS0\0"                                               \
526         "fdtaddr=0x780000\0"                                            \
527         "kernel_addr=ff800000\0"                                        \
528         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
529         "setbootargs=setenv bootargs "                                  \
530                 "root=${rootdev} rw console=${console},"                \
531                         "${baudrate} ${othbootargs}\0"                  \
532         "setipargs=setenv bootargs root=${rootdev} rw "                 \
533                         "nfsroot=${serverip}:${rootpath} "              \
534                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
535                         "${netmask}:${hostname}:${netdev}:off "         \
536                         "console=${console},${baudrate} ${othbootargs}\0" \
537         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
538         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
539         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
540         "\0"
541
542 #define CONFIG_NFSBOOTCOMMAND                                           \
543         "setenv rootdev /dev/nfs;"                                      \
544         "run setipargs;run addmtd;"                                     \
545         "tftp ${loadaddr} ${bootfile};"                         \
546         "tftp ${fdtaddr} ${fdtfile};"                                   \
547         "fdt addr ${fdtaddr};"                                          \
548         "bootm ${loadaddr} - ${fdtaddr}"
549
550 /* UBI Support */
551 #define CONFIG_CMD_NAND_TRIMFFS
552 #define CONFIG_CMD_UBI
553 #define CONFIG_CMD_UBIFS
554 #define CONFIG_RBTREE
555 #define CONFIG_LZO
556 #define CONFIG_MTD_PARTITIONS
557
558 /* bootcount support */
559 #define CONFIG_BOOTCOUNT_LIMIT
560 #define CONFIG_BOOTCOUNT_I2C
561 #define CONFIG_BOOTCOUNT_ALEN   1
562 #define CONFIG_SYS_BOOTCOUNT_ADDR       0x9
563
564 #define CONFIG_VERSION_VARIABLE
565
566 #define CONFIG_IMAGE_FORMAT_LEGACY
567 #define CONFIG_CMD_FDT
568 #define CONFIG_CMD_HASH
569 #define CONFIG_SHA1
570 #define CONFIG_SHA256
571
572 #endif  /* __CONFIG_H */