include/configs/ids8313.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (c) 2011 IDS GmbH, Germany
   8  * Sergej Stepanov <ste@ids.de>
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_FSL_ELBC
  18
  19 #define CONFIG_BOOT_RETRY_TIME          900
  20 #define CONFIG_BOOT_RETRY_MIN           30
  21 #define CONFIG_RESET_TO_RETRY
  22
  23 #define CONFIG_83XX_CLKIN               66000000        /* in Hz */
  24 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  25
  26 #define CONFIG_SYS_IMMR         0xF0000000
  27
  28 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  29 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  30
  31 /*
  32  * Hardware Reset Configuration Word
  33  * if CLKIN is 66.000MHz, then
  34  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  35  */
  36 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  37                              HRCWL_DDR_TO_SCB_CLK_2X1 |\
  38                              HRCWL_CSB_TO_CLKIN_2X1 |\
  39                              HRCWL_CORE_TO_CSB_2X1)
  40
  41 #define CONFIG_SYS_HRCW_HIGH    (HRCWH_PCI_HOST |\
  42                                  HRCWH_CORE_ENABLE |\
  43                                  HRCWH_FROM_0XFFF00100 |\
  44                                  HRCWH_BOOTSEQ_DISABLE |\
  45                                  HRCWH_SW_WATCHDOG_DISABLE |\
  46                                  HRCWH_ROM_LOC_LOCAL_8BIT |\
  47                                  HRCWH_RL_EXT_LEGACY |\
  48                                  HRCWH_TSEC1M_IN_MII |\
  49                                  HRCWH_TSEC2M_IN_MII |\
  50                                  HRCWH_BIG_ENDIAN)
  51
  52 #define CONFIG_SYS_SICRH        0x00000000
  53 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
  54
  55 #define CONFIG_HWCONFIG
  56
  57 #define CONFIG_SYS_HID0_INIT    0x000000000
  58 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
  59                                  HID0_ENABLE_INSTRUCTION_CACHE |\
  60                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  61
  62 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  63
  64 /*
  65  * Definitions for initial stack pointer and data area (in DCACHE )
  66  */
  67 #define CONFIG_SYS_INIT_RAM_LOCK
  68 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
  69 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
  70 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
  71 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
  72                                          - CONFIG_SYS_GBL_DATA_SIZE)
  73 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  74
  75 /*
  76  * Local Bus LCRR and LBCR regs
  77  */
  78 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
  79 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
  80 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
  81                                          (0xFF << LBCR_BMT_SHIFT) |\
  82                                          0xF)
  83
  84 #define CONFIG_SYS_LBC_MRTPR            0x20000000
  85
  86 /*
  87  * Internal Definitions
  88  */
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_SYS_DDR_BASE             0x00000000
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95
  96 /*
  97  * Manually set up DDR parameters,
  98  * as this board has not the SPD connected to I2C.
  99  */
 100 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 101 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
 102                                          0x00010000 |\
 103                                          CSCONFIG_ROW_BIT_13 |\
 104                                          CSCONFIG_COL_BIT_10)
 105
 106 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
 107                                          CSCONFIG_BANK_BIT_3)
 108
 109 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
 110 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
 111                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
 112                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
 113                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
 114                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
 115                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
 116                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 117                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 118 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
 119                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
 120                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
 121                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
 122                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
 123                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
 124                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
 125                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
 126 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
 127                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
 128                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
 129                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
 130                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
 131                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
 132                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 133
 134 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
 135                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 136
 137 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
 138                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
 139                                          SDRAM_CFG_DBW_32 |\
 140                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
 141
 142 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 143 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
 144                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
 145 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 146 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
 147 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
 148                                          DDRCDR_PZ_NOMZ |\
 149                                          DDRCDR_NZ_NOMZ |\
 150                                          DDRCDR_ODT |\
 151                                          DDRCDR_M_ODR |\
 152                                          DDRCDR_Q_DRN)
 153
 154 /*
 155  * on-board devices
 156  */
 157 #define CONFIG_TSEC1
 158 #define CONFIG_TSEC2
 159
 160 /*
 161  * NOR FLASH setup
 162  */
 163 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 164 #define CONFIG_FLASH_SHOW_PROGRESS      50
 165
 166 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 167 #define CONFIG_SYS_FLASH_SIZE           8
 168
 169 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 170 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016
 171
 172 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |\
 173                                          BR_PS_8 |\
 174                                          BR_MS_GPCM |\
 175                                          BR_V)
 176
 177 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
 178                                          OR_GPCM_SCY_10 |\
 179                                          OR_GPCM_EHTR |\
 180                                          OR_GPCM_TRLX |\
 181                                          OR_GPCM_CSNT |\
 182                                          OR_GPCM_EAD)
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 184 #define CONFIG_SYS_MAX_FLASH_SECT       128
 185
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 188
 189 /*
 190  * NAND FLASH setup
 191  */
 192 #define CONFIG_SYS_NAND_BASE            0xE1000000
 193 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 194 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 195 #define CONFIG_NAND_FSL_ELBC
 196 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
 197 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 198 #define NAND_CACHE_PAGES                64
 199
 200 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 201 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
 202 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 203 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR1_PRELIM
 204
 205 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_NAND_BASE) |\
 206                                  (2<<BR_DECC_SHIFT) |\
 207                                  BR_PS_8 |\
 208                                  BR_MS_FCM |\
 209                                  BR_V)
 210
 211 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000 |\
 212                                  OR_FCM_PGS |\
 213                                  OR_FCM_CSCT |\
 214                                  OR_FCM_CST |\
 215                                  OR_FCM_CHT |\
 216                                  OR_FCM_SCY_4 |\
 217                                  OR_FCM_TRLX |\
 218                                  OR_FCM_EHTR |\
 219                                  OR_FCM_RST)
 220
 221 /*
 222  * MRAM setup
 223  */
 224 #define CONFIG_SYS_MRAM_BASE            0xE2000000
 225 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
 226 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_MRAM_BASE
 227 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* 128 Kb  */
 228
 229 #define CONFIG_SYS_OR_TIMING_MRAM
 230
 231 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_MRAM_BASE |\
 232                                          BR_PS_8 |\
 233                                          BR_MS_GPCM |\
 234                                          BR_V)
 235
 236 #define CONFIG_SYS_OR2_PRELIM           0xFFFE0C74
 237
 238 /*
 239  * CPLD setup
 240  */
 241 #define CONFIG_SYS_CPLD_BASE            0xE3000000
 242 #define CONFIG_SYS_CPLD_SIZE            0x8000
 243 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CPLD_BASE
 244 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E
 245
 246 #define CONFIG_SYS_OR_TIMING_MRAM
 247
 248 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_CPLD_BASE |\
 249                                          BR_PS_8 |\
 250                                          BR_MS_GPCM |\
 251                                          BR_V)
 252
 253 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8814
 254
 255 /*
 256  * HW-Watchdog
 257  */
 258 #define CONFIG_WATCHDOG         1
 259 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
 260
 261 /*
 262  * I2C setup
 263  */
 264 #define CONFIG_SYS_I2C
 265 #define CONFIG_SYS_I2C_FSL
 266 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 267 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 268 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 269 #define CONFIG_RTC_PCF8563
 270 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 271
 272 /*
 273  * Ethernet setup
 274  */
 275 #ifdef CONFIG_TSEC1
 276 #define CONFIG_HAS_ETH0
 277 #define CONFIG_TSEC1_NAME               "TSEC0"
 278 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 279 #define TSEC1_PHY_ADDR                  0x1
 280 #define TSEC1_FLAGS                     TSEC_GIGABIT
 281 #define TSEC1_PHYIDX                    0
 282 #endif
 283
 284 #ifdef CONFIG_TSEC2
 285 #define CONFIG_HAS_ETH1
 286 #define CONFIG_TSEC2_NAME               "TSEC1"
 287 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 288 #define TSEC2_PHY_ADDR                  0x3
 289 #define TSEC2_FLAGS                     TSEC_GIGABIT
 290 #define TSEC2_PHYIDX                    0
 291 #endif
 292 #define CONFIG_ETHPRIME         "TSEC1"
 293
 294 /*
 295  * Serial Port
 296  */
 297 #define CONFIG_SYS_NS16550_SERIAL
 298 #define CONFIG_SYS_NS16550_REG_SIZE     1
 299
 300 #define CONFIG_SYS_BAUDRATE_TABLE       \
 301         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 304 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 305
 306 #define CONFIG_HAS_FSL_DR_USB
 307 #define CONFIG_SYS_SCCR_USBDRCM 3
 308
 309 /*
 310  * BAT's
 311  */
 312 #define CONFIG_HIGH_BATS
 313
 314 /* DDR @ 0x00000000 */
 315 #define CONFIG_SYS_IBAT0L               (CONFIG_SYS_SDRAM_BASE |\
 316                                          BATL_PP_10)
 317 #define CONFIG_SYS_IBAT0U               (CONFIG_SYS_SDRAM_BASE |\
 318                                          BATU_BL_256M |\
 319                                          BATU_VS |\
 320                                          BATU_VP)
 321 #define CONFIG_SYS_DBAT0L               CONFIG_SYS_IBAT0L
 322 #define CONFIG_SYS_DBAT0U               CONFIG_SYS_IBAT0U
 323
 324 /* Initial RAM @ 0xFD000000 */
 325 #define CONFIG_SYS_IBAT1L               (CONFIG_SYS_INIT_RAM_ADDR |\
 326                                          BATL_PP_10 |\
 327                                          BATL_GUARDEDSTORAGE)
 328 #define CONFIG_SYS_IBAT1U               (CONFIG_SYS_INIT_RAM_ADDR |\
 329                                          BATU_BL_256K |\
 330                                          BATU_VS |\
 331                                          BATU_VP)
 332 #define CONFIG_SYS_DBAT1L               CONFIG_SYS_IBAT1L
 333 #define CONFIG_SYS_DBAT1U               CONFIG_SYS_IBAT1U
 334
 335 /* FLASH @ 0xFF800000 */
 336 #define CONFIG_SYS_IBAT2L               (CONFIG_SYS_FLASH_BASE |\
 337                                          BATL_PP_10 |\
 338                                          BATL_GUARDEDSTORAGE)
 339 #define CONFIG_SYS_IBAT2U               (CONFIG_SYS_FLASH_BASE |\
 340                                          BATU_BL_8M |\
 341                                          BATU_VS |\
 342                                          BATU_VP)
 343 #define CONFIG_SYS_DBAT2L               (CONFIG_SYS_FLASH_BASE |\
 344                                          BATL_PP_10 |\
 345                                          BATL_CACHEINHIBIT |\
 346                                          BATL_GUARDEDSTORAGE)
 347 #define CONFIG_SYS_DBAT2U               CONFIG_SYS_IBAT2U
 348
 349 #define CONFIG_SYS_IBAT3L               (0)
 350 #define CONFIG_SYS_IBAT3U               (0)
 351 #define CONFIG_SYS_DBAT3L               CONFIG_SYS_IBAT3L
 352 #define CONFIG_SYS_DBAT3U               CONFIG_SYS_IBAT3U
 353
 354 #define CONFIG_SYS_IBAT4L               (0)
 355 #define CONFIG_SYS_IBAT4U               (0)
 356 #define CONFIG_SYS_DBAT4L               CONFIG_SYS_IBAT4L
 357 #define CONFIG_SYS_DBAT4U               CONFIG_SYS_IBAT4U
 358
 359 /* IMMRBAR @ 0xF0000000 */
 360 #define CONFIG_SYS_IBAT5L               (CONFIG_SYS_IMMR |\
 361                                          BATL_PP_10 |\
 362                                          BATL_CACHEINHIBIT |\
 363                                          BATL_GUARDEDSTORAGE)
 364 #define CONFIG_SYS_IBAT5U               (CONFIG_SYS_IMMR |\
 365                                          BATU_BL_128M |\
 366                                          BATU_VS |\
 367                                          BATU_VP)
 368 #define CONFIG_SYS_DBAT5L               CONFIG_SYS_IBAT5L
 369 #define CONFIG_SYS_DBAT5U               CONFIG_SYS_IBAT5U
 370
 371 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
 372 #define CONFIG_SYS_IBAT6L               (0xE0000000 |\
 373                                          BATL_PP_10 |\
 374                                          BATL_GUARDEDSTORAGE)
 375 #define CONFIG_SYS_IBAT6U               (0xE0000000 |\
 376                                          BATU_BL_256M |\
 377                                          BATU_VS |\
 378                                          BATU_VP)
 379 #define CONFIG_SYS_DBAT6L               CONFIG_SYS_IBAT6L
 380 #define CONFIG_SYS_DBAT6U               CONFIG_SYS_IBAT6U
 381
 382 #define CONFIG_SYS_IBAT7L               (0)
 383 #define CONFIG_SYS_IBAT7U               (0)
 384 #define CONFIG_SYS_DBAT7L               CONFIG_SYS_IBAT7L
 385 #define CONFIG_SYS_DBAT7U               CONFIG_SYS_IBAT7U
 386
 387 /*
 388  * U-Boot environment setup
 389  */
 390 #define CONFIG_BOOTP_BOOTFILESIZE
 391
 392 /*
 393  * The reserved memory
 394  */
 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 396 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 397 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
 398
 399 /*
 400  * Environment Configuration
 401  */
 402 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 403                                 + CONFIG_SYS_MONITOR_LEN)
 404 #define CONFIG_ENV_SIZE         0x20000
 405 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 406 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 407
 408 #define CONFIG_NETDEV                   eth1
 409 #define CONFIG_HOSTNAME         "ids8313"
 410 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
 411 #define CONFIG_BOOTFILE         "ids8313/uImage"
 412 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
 413 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
 414 #define CONFIG_LOADADDR         0x400000
 415 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
 416
 417 /* Initial Memory map for Linux*/
 418 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 419
 420 /*
 421  * Miscellaneous configurable options
 422  */
 423 #define CONFIG_SYS_CBSIZE               1024
 424 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 425
 426 #define CONFIG_SYS_MEMTEST_START        0x00001000
 427 #define CONFIG_SYS_MEMTEST_END          0x00C00000
 428
 429 #define CONFIG_SYS_LOAD_ADDR            0x100000
 430 #define CONFIG_LOADS_ECHO
 431 #define CONFIG_TIMESTAMP
 432 #define CONFIG_PREBOOT                  "echo;" \
 433                                         "echo Type \\\"run nfsboot\\\" " \
 434                                         "to mount root filesystem over NFS;echo"
 435 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
 436 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 437
 438 #define CONFIG_JFFS2_NAND
 439 #define CONFIG_JFFS2_DEV                "0"
 440
 441 /* mtdparts command line support */
 442
 443 #define CONFIG_EXTRA_ENV_SETTINGS \
 444         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 445         "ethprime=TSEC1\0"                                              \
 446         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 447         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
 448                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 449                 " +${filesize}; "                                       \
 450                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 451                 " +${filesize}; "                                       \
 452                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
 453                 " ${filesize}; "                                        \
 454                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 455                 " +${filesize}; "                                       \
 456                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
 457                 " ${filesize}\0"                                        \
 458         "console=ttyS0\0"                                               \
 459         "fdtaddr=0x780000\0"                                            \
 460         "kernel_addr=ff800000\0"                                        \
 461         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
 462         "setbootargs=setenv bootargs "                                  \
 463                 "root=${rootdev} rw console=${console},"                \
 464                         "${baudrate} ${othbootargs}\0"                  \
 465         "setipargs=setenv bootargs root=${rootdev} rw "                 \
 466                         "nfsroot=${serverip}:${rootpath} "              \
 467                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
 468                         "${netmask}:${hostname}:${netdev}:off "         \
 469                         "console=${console},${baudrate} ${othbootargs}\0" \
 470         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 471         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"                                    \
 472         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"                                \
 473         "\0"
 474
 475 #define CONFIG_NFSBOOTCOMMAND                                           \
 476         "setenv rootdev /dev/nfs;"                                      \
 477         "run setipargs;run addmtd;"                                     \
 478         "tftp ${loadaddr} ${bootfile};"                         \
 479         "tftp ${fdtaddr} ${fdtfile};"                                   \
 480         "fdt addr ${fdtaddr};"                                          \
 481         "bootm ${loadaddr} - ${fdtaddr}"
 482
 483 /* UBI Support */
 484
 485 #endif  /* __CONFIG_H */