1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * Sergej Stepanov <ste@ids.de>
14 #include <linux/stringify.h>
17 * High Level Configuration Options
20 #define CONFIG_SYS_SICRH 0x00000000
21 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
23 #define CONFIG_HWCONFIG
26 * Definitions for initial stack pointer and data area (in DCACHE )
28 #define CONFIG_SYS_INIT_RAM_LOCK
29 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
30 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
33 * Internal Definitions
38 #define CONFIG_SYS_SDRAM_BASE 0x00000000
41 * Manually set up DDR parameters,
42 * as this board has not the SPD connected to I2C.
44 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
45 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
47 CSCONFIG_ROW_BIT_13 |\
50 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
53 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
54 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
55 (3 << TIMING_CFG0_WRT_SHIFT) |\
56 (3 << TIMING_CFG0_RRT_SHIFT) |\
57 (3 << TIMING_CFG0_WWT_SHIFT) |\
58 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
59 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
60 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
61 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
62 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
63 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
64 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
65 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
66 (4 << TIMING_CFG1_REFREC_SHIFT) |\
67 (4 << TIMING_CFG1_WRREC_SHIFT) |\
68 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
69 (2 << TIMING_CFG1_WRTORD_SHIFT))
70 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
71 (5 << TIMING_CFG2_CPO_SHIFT) |\
72 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
73 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
74 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
75 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
76 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
78 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
79 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
81 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
82 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
84 SDRAM_CFG_SDRAM_TYPE_DDR2)
86 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
87 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
88 (0x0242 << SDRAM_MODE_SD_SHIFT))
89 #define CONFIG_SYS_DDR_MODE_2 0x00000000
90 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
91 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
107 #define CONFIG_FLASH_SHOW_PROGRESS 50
109 #define CONFIG_SYS_FLASH_BASE 0xFF800000
110 #define CONFIG_SYS_FLASH_SIZE 8
115 #define CONFIG_SYS_NAND_BASE 0xE1000000
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1
117 #define NAND_CACHE_PAGES 64
123 #define CONFIG_SYS_MRAM_BASE 0xE2000000
124 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
126 #define CONFIG_SYS_OR_TIMING_MRAM
132 #define CONFIG_SYS_CPLD_BASE 0xE3000000
133 #define CONFIG_SYS_CPLD_SIZE 0x8000
135 #define CONFIG_SYS_OR_TIMING_MRAM
141 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
146 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
152 #define CONFIG_TSEC1_NAME "TSEC0"
153 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
154 #define TSEC1_PHY_ADDR 0x1
155 #define TSEC1_FLAGS TSEC_GIGABIT
156 #define TSEC1_PHYIDX 0
160 #define CONFIG_TSEC2_NAME "TSEC1"
161 #define TSEC2_PHY_ADDR 0x3
162 #define TSEC2_FLAGS TSEC_GIGABIT
163 #define TSEC2_PHYIDX 0
169 #define CONFIG_SYS_NS16550_SERIAL
170 #define CONFIG_SYS_NS16550_REG_SIZE 1
172 #define CONFIG_SYS_BAUDRATE_TABLE \
173 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
176 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
178 #define CONFIG_SYS_SCCR_USBDRCM 3
181 * U-Boot environment setup
185 * The reserved memory
187 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
190 * Environment Configuration
193 #define CONFIG_NETDEV eth1
194 #define CONFIG_HOSTNAME "ids8313"
195 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
196 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
197 #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
198 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
200 /* Initial Memory map for Linux*/
201 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
204 * Miscellaneous configurable options
207 #define CONFIG_LOADS_ECHO
208 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
210 /* mtdparts command line support */
212 #define CONFIG_EXTRA_ENV_SETTINGS \
213 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
215 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
216 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
217 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
219 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
221 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
223 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
225 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
228 "fdtaddr=0x780000\0" \
229 "kernel_addr=ff800000\0" \
230 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
231 "setbootargs=setenv bootargs " \
232 "root=${rootdev} rw console=${console}," \
233 "${baudrate} ${othbootargs}\0" \
234 "setipargs=setenv bootargs root=${rootdev} rw " \
235 "nfsroot=${serverip}:${rootpath} " \
236 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
237 "${netmask}:${hostname}:${netdev}:off " \
238 "console=${console},${baudrate} ${othbootargs}\0" \
239 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
244 #endif /* __CONFIG_H */