include/configs/ids8313.h

   1 /*
   2  * (C) Copyright 2013
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * Based on:
   6  * Copyright (c) 2011 IDS GmbH, Germany
   7  * Sergej Stepanov <ste@ids.de>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_MPC831x
  19 #define CONFIG_MPC8313
  20 #define CONFIG_IDS8313
  21
  22 #define CONFIG_SYS_GENERIC_BOARD
  23
  24 #define CONFIG_FSL_ELBC
  25
  26 #define CONFIG_MISC_INIT_R
  27
  28 #define CONFIG_AUTOBOOT_KEYED
  29 #define CONFIG_AUTOBOOT_PROMPT  \
  30         "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
  31 #define CONFIG_AUTOBOOT_DELAY_STR       "ids"
  32 #define CONFIG_BOOT_RETRY_TIME          900
  33 #define CONFIG_BOOT_RETRY_MIN           30
  34 #define CONFIG_BOOTDELAY                1
  35 #define CONFIG_RESET_TO_RETRY
  36
  37 #define CONFIG_83XX_CLKIN               66000000        /* in Hz */
  38 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  39
  40 #define CONFIG_SYS_IMMR         0xF0000000
  41
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  43 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  * if CLKIN is 66.000MHz, then
  48  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  49  */
  50 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  51                              HRCWL_DDR_TO_SCB_CLK_2X1 |\
  52                              HRCWL_CSB_TO_CLKIN_2X1 |\
  53                              HRCWL_CORE_TO_CSB_2X1)
  54
  55 #define CONFIG_SYS_HRCW_HIGH    (HRCWH_PCI_HOST |\
  56                                  HRCWH_CORE_ENABLE |\
  57                                  HRCWH_FROM_0XFFF00100 |\
  58                                  HRCWH_BOOTSEQ_DISABLE |\
  59                                  HRCWH_SW_WATCHDOG_DISABLE |\
  60                                  HRCWH_ROM_LOC_LOCAL_8BIT |\
  61                                  HRCWH_RL_EXT_LEGACY |\
  62                                  HRCWH_TSEC1M_IN_MII |\
  63                                  HRCWH_TSEC2M_IN_MII |\
  64                                  HRCWH_BIG_ENDIAN)
  65
  66 #define CONFIG_SYS_SICRH        0x00000000
  67 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
  68
  69 #define CONFIG_HWCONFIG
  70
  71 #define CONFIG_SYS_HID0_INIT    0x000000000
  72 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
  73                                  HID0_ENABLE_INSTRUCTION_CACHE |\
  74                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  75
  76 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  77
  78 /*
  79  * Definitions for initial stack pointer and data area (in DCACHE )
  80  */
  81 #define CONFIG_SYS_INIT_RAM_LOCK
  82 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
  83 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
  84 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
  85 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
  86                                          - CONFIG_SYS_GBL_DATA_SIZE)
  87 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  88
  89 /*
  90  * Local Bus LCRR and LBCR regs
  91  */
  92 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
  93 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
  94 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
  95                                          (0xFF << LBCR_BMT_SHIFT) |\
  96                                          0xF)
  97
  98 #define CONFIG_SYS_LBC_MRTPR            0x20000000
  99
 100 /*
 101  * Internal Definitions
 102  */
 103 /*
 104  * DDR Setup
 105  */
 106 #define CONFIG_SYS_DDR_BASE             0x00000000
 107 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 109
 110 /*
 111  * Manually set up DDR parameters,
 112  * as this board has not the SPD connected to I2C.
 113  */
 114 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 115 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
 116                                          0x00010000 |\
 117                                          CSCONFIG_ROW_BIT_13 |\
 118                                          CSCONFIG_COL_BIT_10)
 119
 120 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
 121                                          CSCONFIG_BANK_BIT_3)
 122
 123 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
 124 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
 125                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
 126                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
 127                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
 128                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
 129                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
 130                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 131                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 132 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
 133                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
 134                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
 135                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
 136                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
 137                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
 138                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
 139                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
 140 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
 141                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
 142                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
 143                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
 144                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
 145                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
 146                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 147
 148 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
 149                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 150
 151 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
 152                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
 153                                          SDRAM_CFG_DBW_32 |\
 154                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
 155
 156 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 157 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
 158                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
 159 #define CONFIG_SYS_DDR_MODE_2           0x00000000
 160 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
 161 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
 162                                          DDRCDR_PZ_NOMZ |\
 163                                          DDRCDR_NZ_NOMZ |\
 164                                          DDRCDR_ODT |\
 165                                          DDRCDR_M_ODR |\
 166                                          DDRCDR_Q_DRN)
 167
 168 /*
 169  * on-board devices
 170  */
 171 #define CONFIG_TSEC1
 172 #define CONFIG_TSEC2
 173 #define CONFIG_TSEC_ENET
 174 #define CONFIG_NET_MULTI
 175 #define CONFIG_HARD_SPI
 176 #define CONFIG_HARD_I2C
 177
 178 /*
 179  * NOR FLASH setup
 180  */
 181 #define CONFIG_SYS_FLASH_CFI
 182 #define CONFIG_FLASH_CFI_DRIVER
 183 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
 184 #define CONFIG_FLASH_SHOW_PROGRESS      50
 185 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 186
 187 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 188 #define CONFIG_SYS_FLASH_SIZE           8
 189 #define CONFIG_SYS_FLASH_PROTECTION
 190
 191 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 192 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016
 193
 194 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |\
 195                                          BR_PS_8 |\
 196                                          BR_MS_GPCM |\
 197                                          BR_V)
 198
 199 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
 200                                          OR_GPCM_SCY_10 |\
 201                                          OR_GPCM_EHTR |\
 202                                          OR_GPCM_TRLX |\
 203                                          OR_GPCM_CSNT |\
 204                                          OR_GPCM_EAD)
 205 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 206 #define CONFIG_SYS_MAX_FLASH_SECT       128
 207
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 210
 211 /*
 212  * NAND FLASH setup
 213  */
 214 #define CONFIG_SYS_NAND_BASE            0xE1000000
 215 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 216 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 217 #define CONFIG_NAND_FSL_ELBC
 218 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
 219 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 220 #define NAND_CACHE_PAGES                64
 221
 222 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 223 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
 224 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 225 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR1_PRELIM
 226
 227 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_NAND_BASE) |\
 228                                  (2<<BR_DECC_SHIFT) |\
 229                                  BR_PS_8 |\
 230                                  BR_MS_FCM |\
 231                                  BR_V)
 232
 233 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000 |\
 234                                  OR_FCM_PGS |\
 235                                  OR_FCM_CSCT |\
 236                                  OR_FCM_CST |\
 237                                  OR_FCM_CHT |\
 238                                  OR_FCM_SCY_4 |\
 239                                  OR_FCM_TRLX |\
 240                                  OR_FCM_EHTR |\
 241                                  OR_FCM_RST)
 242
 243 /*
 244  * MRAM setup
 245  */
 246 #define CONFIG_SYS_MRAM_BASE            0xE2000000
 247 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
 248 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_MRAM_BASE
 249 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* 128 Kb  */
 250
 251 #define CONFIG_SYS_OR_TIMING_MRAM
 252
 253 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_MRAM_BASE |\
 254                                          BR_PS_8 |\
 255                                          BR_MS_GPCM |\
 256                                          BR_V)
 257
 258 #define CONFIG_SYS_OR2_PRELIM           0xFFFE0C74
 259
 260 /*
 261  * CPLD setup
 262  */
 263 #define CONFIG_SYS_CPLD_BASE            0xE3000000
 264 #define CONFIG_SYS_CPLD_SIZE            0x8000
 265 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CPLD_BASE
 266 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E
 267
 268 #define CONFIG_SYS_OR_TIMING_MRAM
 269
 270 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_CPLD_BASE |\
 271                                          BR_PS_8 |\
 272                                          BR_MS_GPCM |\
 273                                          BR_V)
 274
 275 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8814
 276
 277 /*
 278  * HW-Watchdog
 279  */
 280 #define CONFIG_WATCHDOG         1
 281 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
 282
 283 /*
 284  * I2C setup
 285  */
 286 #define CONFIG_CMD_I2C
 287 #define CONFIG_SYS_I2C
 288 #define CONFIG_SYS_I2C_FSL
 289 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 290 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 291 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 292 #define CONFIG_RTC_PCF8563
 293 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 294
 295 /*
 296  * SPI setup
 297  */
 298 #ifdef CONFIG_HARD_SPI
 299 #define CONFIG_MPC8XXX_SPI
 300 #define CONFIG_CMD_SPI
 301 #define CONFIG_SYS_GPIO1_PRELIM
 302 #define CONFIG_SYS_GPIO1_DIR            0x00000001
 303 #define CONFIG_SYS_GPIO1_DAT            0x00000001
 304 #endif
 305
 306 /*
 307  * Ethernet setup
 308  */
 309 #ifdef CONFIG_TSEC1
 310 #define CONFIG_HAS_ETH0
 311 #define CONFIG_TSEC1_NAME               "TSEC0"
 312 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 313 #define TSEC1_PHY_ADDR                  0x1
 314 #define TSEC1_FLAGS                     TSEC_GIGABIT
 315 #define TSEC1_PHYIDX                    0
 316 #endif
 317
 318 #ifdef CONFIG_TSEC2
 319 #define CONFIG_HAS_ETH1
 320 #define CONFIG_TSEC2_NAME               "TSEC1"
 321 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 322 #define TSEC2_PHY_ADDR                  0x3
 323 #define TSEC2_FLAGS                     TSEC_GIGABIT
 324 #define TSEC2_PHYIDX                    0
 325 #endif
 326 #define CONFIG_ETHPRIME         "TSEC1"
 327
 328 /*
 329  * Serial Port
 330  */
 331 #define CONFIG_CONS_INDEX               1
 332 #define CONFIG_SYS_NS16550
 333 #define CONFIG_SYS_NS16550_SERIAL
 334 #define CONFIG_SYS_NS16550_REG_SIZE     1
 335
 336 #define CONFIG_SYS_BAUDRATE_TABLE       \
 337         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 338 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 339 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 340 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 341
 342 #define CONFIG_HAS_FSL_DR_USB
 343 #define CONFIG_SYS_SCCR_USBDRCM 3
 344
 345 /*
 346  * BAT's
 347  */
 348 #define CONFIG_HIGH_BATS
 349
 350 /* DDR @ 0x00000000 */
 351 #define CONFIG_SYS_IBAT0L               (CONFIG_SYS_SDRAM_BASE |\
 352                                          BATL_PP_10)
 353 #define CONFIG_SYS_IBAT0U               (CONFIG_SYS_SDRAM_BASE |\
 354                                          BATU_BL_256M |\
 355                                          BATU_VS |\
 356                                          BATU_VP)
 357 #define CONFIG_SYS_DBAT0L               CONFIG_SYS_IBAT0L
 358 #define CONFIG_SYS_DBAT0U               CONFIG_SYS_IBAT0U
 359
 360 /* Initial RAM @ 0xFD000000 */
 361 #define CONFIG_SYS_IBAT1L               (CONFIG_SYS_INIT_RAM_ADDR |\
 362                                          BATL_PP_10 |\
 363                                          BATL_GUARDEDSTORAGE)
 364 #define CONFIG_SYS_IBAT1U               (CONFIG_SYS_INIT_RAM_ADDR |\
 365                                          BATU_BL_256K |\
 366                                          BATU_VS |\
 367                                          BATU_VP)
 368 #define CONFIG_SYS_DBAT1L               CONFIG_SYS_IBAT1L
 369 #define CONFIG_SYS_DBAT1U               CONFIG_SYS_IBAT1U
 370
 371 /* FLASH @ 0xFF800000 */
 372 #define CONFIG_SYS_IBAT2L               (CONFIG_SYS_FLASH_BASE |\
 373                                          BATL_PP_10 |\
 374                                          BATL_GUARDEDSTORAGE)
 375 #define CONFIG_SYS_IBAT2U               (CONFIG_SYS_FLASH_BASE |\
 376                                          BATU_BL_8M |\
 377                                          BATU_VS |\
 378                                          BATU_VP)
 379 #define CONFIG_SYS_DBAT2L               (CONFIG_SYS_FLASH_BASE |\
 380                                          BATL_PP_10 |\
 381                                          BATL_CACHEINHIBIT |\
 382                                          BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_DBAT2U               CONFIG_SYS_IBAT2U
 384
 385 #define CONFIG_SYS_IBAT3L               (0)
 386 #define CONFIG_SYS_IBAT3U               (0)
 387 #define CONFIG_SYS_DBAT3L               CONFIG_SYS_IBAT3L
 388 #define CONFIG_SYS_DBAT3U               CONFIG_SYS_IBAT3U
 389
 390 #define CONFIG_SYS_IBAT4L               (0)
 391 #define CONFIG_SYS_IBAT4U               (0)
 392 #define CONFIG_SYS_DBAT4L               CONFIG_SYS_IBAT4L
 393 #define CONFIG_SYS_DBAT4U               CONFIG_SYS_IBAT4U
 394
 395 /* IMMRBAR @ 0xF0000000 */
 396 #define CONFIG_SYS_IBAT5L               (CONFIG_SYS_IMMR |\
 397                                          BATL_PP_10 |\
 398                                          BATL_CACHEINHIBIT |\
 399                                          BATL_GUARDEDSTORAGE)
 400 #define CONFIG_SYS_IBAT5U               (CONFIG_SYS_IMMR |\
 401                                          BATU_BL_128M |\
 402                                          BATU_VS |\
 403                                          BATU_VP)
 404 #define CONFIG_SYS_DBAT5L               CONFIG_SYS_IBAT5L
 405 #define CONFIG_SYS_DBAT5U               CONFIG_SYS_IBAT5U
 406
 407 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
 408 #define CONFIG_SYS_IBAT6L               (0xE0000000 |\
 409                                          BATL_PP_10 |\
 410                                          BATL_GUARDEDSTORAGE)
 411 #define CONFIG_SYS_IBAT6U               (0xE0000000 |\
 412                                          BATU_BL_256M |\
 413                                          BATU_VS |\
 414                                          BATU_VP)
 415 #define CONFIG_SYS_DBAT6L               CONFIG_SYS_IBAT6L
 416 #define CONFIG_SYS_DBAT6U               CONFIG_SYS_IBAT6U
 417
 418 #define CONFIG_SYS_IBAT7L               (0)
 419 #define CONFIG_SYS_IBAT7U               (0)
 420 #define CONFIG_SYS_DBAT7L               CONFIG_SYS_IBAT7L
 421 #define CONFIG_SYS_DBAT7U               CONFIG_SYS_IBAT7U
 422
 423 /*
 424  * U-Boot environment setup
 425  */
 426 #include <config_cmd_default.h>
 427
 428 #define CONFIG_CMD_DHCP
 429 #define CONFIG_CMD_PING
 430 #define CONFIG_CMD_NFS
 431 #define CONFIG_CMD_NAND
 432 #define CONFIG_CMD_FLASH
 433 #define CONFIG_CMD_SNTP
 434 #define CONFIG_CMD_MII
 435 #define CONFIG_CMD_DATE
 436 #define CONFIG_CMDLINE_EDITING
 437 #define CONFIG_CMD_EDITENV
 438 #define CONFIG_CMD_JFFS2
 439 #define CONFIG_BOOTP_SUBNETMASK
 440 #define CONFIG_BOOTP_GATEWAY
 441 #define CONFIG_BOOTP_HOSTNAME
 442 #define CONFIG_BOOTP_BOOTPATH
 443 #define CONFIG_BOOTP_BOOTFILESIZE
 444 /* pass open firmware flat tree */
 445 #define CONFIG_OF_LIBFDT
 446 #define CONFIG_OF_BOARD_SETUP
 447 #define CONFIG_OF_STDOUT_VIA_ALIAS
 448
 449 /*
 450  * The reserved memory
 451  */
 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 453 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 454 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
 455
 456 /*
 457  * Environment Configuration
 458  */
 459 #define CONFIG_ENV_IS_IN_FLASH
 460 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
 461                                 + CONFIG_SYS_MONITOR_LEN)
 462 #define CONFIG_ENV_SIZE         0x20000
 463 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 464 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 465
 466
 467 #define CONFIG_NETDEV                   eth1
 468 #define CONFIG_HOSTNAME         ids8313
 469 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
 470 #define CONFIG_BOOTFILE         "ids8313/uImage"
 471 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
 472 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
 473 #define CONFIG_LOADADDR         0x400000
 474 #define CONFIG_CMD_ENV_FLAGS
 475 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
 476
 477 #define CONFIG_BAUDRATE         115200
 478
 479 /* Initial Memory map for Linux*/
 480 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 481
 482 /*
 483  * Miscellaneous configurable options
 484  */
 485 #define CONFIG_SYS_LONGHELP
 486 #define CONFIG_SYS_CBSIZE               1024
 487 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE \
 488                                          + sizeof(CONFIG_SYS_PROMPT)+16)
 489 #define CONFIG_SYS_MAXARGS              16
 490 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 491 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser    */
 492 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 493
 494 #define CONFIG_SYS_MEMTEST_START        0x00001000
 495 #define CONFIG_SYS_MEMTEST_END          0x00C00000
 496
 497 #define CONFIG_SYS_LOAD_ADDR            0x100000
 498 #define CONFIG_MII
 499 #define CONFIG_LOADS_ECHO
 500 #define CONFIG_TIMESTAMP
 501 #define CONFIG_PREBOOT                  "echo;" \
 502                                         "echo Type \\\"run nfsboot\\\" " \
 503                                         "to mount root filesystem over NFS;echo"
 504 #undef  CONFIG_BOOTARGS
 505 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
 506 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 507
 508 #define CONFIG_JFFS2_NAND
 509 #define CONFIG_JFFS2_DEV                "0"
 510
 511 /* mtdparts command line support */
 512 #define CONFIG_CMD_MTDPARTS
 513 #define CONFIG_FLASH_CFI_MTD
 514 #define CONFIG_MTD_DEVICE
 515 #define MTDIDS_DEFAULT          "nor0=ff800000.flash,nand0=e1000000.flash"
 516 #define MTDPARTS_DEFAULT        "mtdparts=ff800000.flash:7m(dum)," \
 517                                         "768k(BOOT-BIN)," \
 518                                         "128k(BOOT-ENV),128k(BOOT-REDENV);" \
 519                                         "e1000000.flash:-(ubi)"
 520
 521 #define CONFIG_EXTRA_ENV_SETTINGS \
 522         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
 523         "ethprime=TSEC1\0"                                              \
 524         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 525         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
 526                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 527                 " +${filesize}; "                                       \
 528                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 529                 " +${filesize}; "                                       \
 530                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
 531                 " ${filesize}; "                                        \
 532                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 533                 " +${filesize}; "                                       \
 534                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
 535                 " ${filesize}\0"                                        \
 536         "console=ttyS0\0"                                               \
 537         "fdtaddr=0x780000\0"                                            \
 538         "kernel_addr=ff800000\0"                                        \
 539         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
 540         "setbootargs=setenv bootargs "                                  \
 541                 "root=${rootdev} rw console=${console},"                \
 542                         "${baudrate} ${othbootargs}\0"                  \
 543         "setipargs=setenv bootargs root=${rootdev} rw "                 \
 544                         "nfsroot=${serverip}:${rootpath} "              \
 545                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
 546                         "${netmask}:${hostname}:${netdev}:off "         \
 547                         "console=${console},${baudrate} ${othbootargs}\0" \
 548         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 549         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 550         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 551         "\0"
 552
 553 #define CONFIG_NFSBOOTCOMMAND                                           \
 554         "setenv rootdev /dev/nfs;"                                      \
 555         "run setipargs;run addmtd;"                                     \
 556         "tftp ${loadaddr} ${bootfile};"                         \
 557         "tftp ${fdtaddr} ${fdtfile};"                                   \
 558         "fdt addr ${fdtaddr};"                                          \
 559         "bootm ${loadaddr} - ${fdtaddr}"
 560
 561 /* UBI Support */
 562 #define CONFIG_CMD_NAND_TRIMFFS
 563 #define CONFIG_CMD_UBI
 564 #define CONFIG_CMD_UBIFS
 565 #define CONFIG_RBTREE
 566 #define CONFIG_LZO
 567 #define CONFIG_MTD_PARTITIONS
 568
 569 /* bootcount support */
 570 #define CONFIG_BOOTCOUNT_LIMIT
 571 #define CONFIG_BOOTCOUNT_I2C
 572 #define CONFIG_BOOTCOUNT_ALEN   1
 573 #define CONFIG_SYS_BOOTCOUNT_ADDR       0x9
 574
 575 #define CONFIG_VERSION_VARIABLE
 576
 577 #define CONFIG_IMAGE_FORMAT_LEGACY
 578 #define CONFIG_CMD_FDT
 579 #define CONFIG_CMD_HASH
 580 #define CONFIG_SHA1
 581 #define CONFIG_SHA256
 582
 583 #endif  /* __CONFIG_H */