1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * Sergej Stepanov <ste@ids.de>
14 #include <linux/stringify.h>
17 * High Level Configuration Options
19 #define CONFIG_BOOT_RETRY_TIME 900
20 #define CONFIG_BOOT_RETRY_MIN 30
21 #define CONFIG_RESET_TO_RETRY
23 #define CONFIG_SYS_SICRH 0x00000000
24 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
26 #define CONFIG_HWCONFIG
29 * Definitions for initial stack pointer and data area (in DCACHE )
31 #define CONFIG_SYS_INIT_RAM_LOCK
32 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
33 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
34 #define CONFIG_SYS_GBL_DATA_SIZE 0x100
35 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
36 - CONFIG_SYS_GBL_DATA_SIZE)
37 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
40 * Internal Definitions
45 #define CONFIG_SYS_SDRAM_BASE 0x00000000
48 * Manually set up DDR parameters,
49 * as this board has not the SPD connected to I2C.
51 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
52 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
54 CSCONFIG_ROW_BIT_13 |\
57 #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
60 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
61 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
62 (3 << TIMING_CFG0_WRT_SHIFT) |\
63 (3 << TIMING_CFG0_RRT_SHIFT) |\
64 (3 << TIMING_CFG0_WWT_SHIFT) |\
65 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
66 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
67 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
68 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
70 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
71 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
72 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
73 (4 << TIMING_CFG1_REFREC_SHIFT) |\
74 (4 << TIMING_CFG1_WRREC_SHIFT) |\
75 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
76 (2 << TIMING_CFG1_WRTORD_SHIFT))
77 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
78 (5 << TIMING_CFG2_CPO_SHIFT) |\
79 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
80 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
81 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
82 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
83 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
85 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
86 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
88 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
89 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
91 SDRAM_CFG_SDRAM_TYPE_DDR2)
93 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
94 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
95 (0x0242 << SDRAM_MODE_SD_SHIFT))
96 #define CONFIG_SYS_DDR_MODE_2 0x00000000
97 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
98 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
114 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
115 #define CONFIG_FLASH_SHOW_PROGRESS 50
117 #define CONFIG_SYS_FLASH_BASE 0xFF800000
118 #define CONFIG_SYS_FLASH_SIZE 8
121 #define CONFIG_SYS_MAX_FLASH_BANKS 1
122 #define CONFIG_SYS_MAX_FLASH_SECT 128
124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
130 #define CONFIG_SYS_NAND_BASE 0xE1000000
131 #define CONFIG_SYS_MAX_NAND_DEVICE 1
132 #define NAND_CACHE_PAGES 64
138 #define CONFIG_SYS_MRAM_BASE 0xE2000000
139 #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
141 #define CONFIG_SYS_OR_TIMING_MRAM
147 #define CONFIG_SYS_CPLD_BASE 0xE3000000
148 #define CONFIG_SYS_CPLD_SIZE 0x8000
150 #define CONFIG_SYS_OR_TIMING_MRAM
156 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
161 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
167 #define CONFIG_HAS_ETH0
168 #define CONFIG_TSEC1_NAME "TSEC0"
169 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
170 #define TSEC1_PHY_ADDR 0x1
171 #define TSEC1_FLAGS TSEC_GIGABIT
172 #define TSEC1_PHYIDX 0
176 #define CONFIG_HAS_ETH1
177 #define CONFIG_TSEC2_NAME "TSEC1"
178 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
179 #define TSEC2_PHY_ADDR 0x3
180 #define TSEC2_FLAGS TSEC_GIGABIT
181 #define TSEC2_PHYIDX 0
183 #define CONFIG_ETHPRIME "TSEC1"
188 #define CONFIG_SYS_NS16550_SERIAL
189 #define CONFIG_SYS_NS16550_REG_SIZE 1
191 #define CONFIG_SYS_BAUDRATE_TABLE \
192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
193 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
194 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
195 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
197 #define CONFIG_HAS_FSL_DR_USB
198 #define CONFIG_SYS_SCCR_USBDRCM 3
201 * U-Boot environment setup
203 #define CONFIG_BOOTP_BOOTFILESIZE
206 * The reserved memory
208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
209 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
212 * Environment Configuration
215 #define CONFIG_NETDEV eth1
216 #define CONFIG_HOSTNAME "ids8313"
217 #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
218 #define CONFIG_BOOTFILE "ids8313/uImage"
219 #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
220 #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
221 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
223 /* Initial Memory map for Linux*/
224 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
227 * Miscellaneous configurable options
229 #define CONFIG_SYS_CBSIZE 1024
230 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
232 #define CONFIG_LOADS_ECHO
233 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
235 /* mtdparts command line support */
237 #define CONFIG_EXTRA_ENV_SETTINGS \
238 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
240 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
241 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
242 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
244 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
246 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
248 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
250 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
253 "fdtaddr=0x780000\0" \
254 "kernel_addr=ff800000\0" \
255 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
256 "setbootargs=setenv bootargs " \
257 "root=${rootdev} rw console=${console}," \
258 "${baudrate} ${othbootargs}\0" \
259 "setipargs=setenv bootargs root=${rootdev} rw " \
260 "nfsroot=${serverip}:${rootpath} " \
261 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
262 "${netmask}:${hostname}:${netdev}:off " \
263 "console=${console},${baudrate} ${othbootargs}\0" \
264 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
265 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
266 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
271 #endif /* __CONFIG_H */