2 * (C) Copyright 2009-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * icon.h - configuration for Mosaixtech ICON (440SPe)
32 * High Level Configuration Options
34 #define CONFIG_ICON 1 /* Board is icon */
35 #define CONFIG_4xx 1 /* ... PPC4xx family */
36 #define CONFIG_440 1 /* ... PPC440 family */
37 #define CONFIG_440SPE 1 /* Specifc SPe support */
38 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
39 #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
42 * Include common defines/options for all AMCC eval boards
44 #define CONFIG_HOSTNAME icon
45 #include "amcc-common.h"
47 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
48 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
51 * Base addresses -- Note these are effective addresses where the
52 * actual resources get mapped (not physical addresses)
54 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
55 #define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
56 #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
58 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
59 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
60 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
62 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
63 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */
64 #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
66 #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
67 #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
68 #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
69 #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
70 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
71 #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
73 /* base address of inbound PCIe window */
74 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
76 /* System RAM mapped to PCI space */
77 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
78 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
79 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
81 #define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */
82 #define CONFIG_SYS_ACE_BASE_PHYS_H 0x4
83 #define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000
85 #define CONFIG_SYS_FLASH_SIZE (64 << 20)
86 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
87 #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
88 #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000
89 #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
90 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
93 * Initial RAM & stack pointer (placed in internal SRAM)
95 #define CONFIG_SYS_TEMP_STACK_OCM 1
96 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
97 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
98 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* end used area */
99 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* sizeof init data */
101 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
102 CONFIG_SYS_GBL_DATA_SIZE)
103 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
109 #undef CONFIG_UART1_CONSOLE
110 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
115 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
116 #define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */
117 #define CONFIG_DDR_ECC /* with ECC support */
118 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
123 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
125 #define CONFIG_I2C_MULTI_BUS
126 #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
128 #define CONFIG_SYS_I2C_MULTI_EEPROMS
129 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
131 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
134 /* I2C bootstrap EEPROM */
135 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
136 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
137 #define CONFIG_4xx_CONFIG_BLOCKSIZE 8
140 #define CONFIG_RTC_M41T11
141 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
142 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
143 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
148 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
151 * Default environment variables
153 #define CONFIG_EXTRA_ENV_SETTINGS \
154 CONFIG_AMCC_DEF_ENV \
155 CONFIG_AMCC_DEF_ENV_POWERPC \
156 CONFIG_AMCC_DEF_ENV_NOR_UPD \
157 "kernel_addr=fc000000\0" \
158 "fdt_addr=fc1e0000\0" \
159 "ramdisk_addr=fc200000\0" \
160 "pciconfighost=1\0" \
161 "pcie_mode=RP:RP:RP\0" \
165 * Commands additional to the ones defined in amcc-common.h
167 #define CONFIG_CMD_CHIP_CONFIG
168 #define CONFIG_CMD_DATE
169 #define CONFIG_CMD_EXT2
170 #define CONFIG_CMD_FAT
171 #define CONFIG_CMD_PCI
172 #define CONFIG_CMD_SDRAM
173 #define CONFIG_CMD_SNTP
175 #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */
176 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
177 #define CONFIG_HAS_ETH0
178 #define CONFIG_PHY_RESET /* reset phy upon startup */
179 #define CONFIG_PHY_RESET_DELAY 1000
180 #define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */
181 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */
186 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
187 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
188 #define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
189 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
191 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */
193 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/
195 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
198 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
199 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */
201 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
202 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
203 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
205 /* Address and size of Redundant Environment Sector */
206 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
207 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
213 #define CONFIG_PCI /* include pci support */
214 #define CONFIG_PCI_PNP /* do pci plug-and-play */
215 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
216 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
217 #define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
219 /* Board-specific PCI */
220 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
221 #undef CONFIG_SYS_PCI_MASTER_INIT
223 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
224 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
227 * Xilinx System ACE support
229 #define CONFIG_SYSTEMACE /* Enable SystemACE support */
230 #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
231 #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
232 #define CONFIG_DOS_PARTITION
235 * External Bus Controller (EBC) Setup
238 /* Memory Bank 0 (Flash) initialization */
239 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
240 EBC_BXAP_TWT_ENCODE(7) | \
241 EBC_BXAP_BCE_DISABLE | \
242 EBC_BXAP_BCT_2TRANS | \
243 EBC_BXAP_CSN_ENCODE(0) | \
244 EBC_BXAP_OEN_ENCODE(0) | \
245 EBC_BXAP_WBN_ENCODE(0) | \
246 EBC_BXAP_WBF_ENCODE(0) | \
247 EBC_BXAP_TH_ENCODE(0) | \
248 EBC_BXAP_RE_DISABLED | \
249 EBC_BXAP_SOR_DELAYED | \
250 EBC_BXAP_BEM_WRITEONLY | \
251 EBC_BXAP_PEN_DISABLED)
252 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
257 /* Memory Bank 1 (Xilinx System ACE controller) initialization */
258 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
259 EBC_BXAP_TWT_ENCODE(4) | \
260 EBC_BXAP_BCE_DISABLE | \
261 EBC_BXAP_BCT_2TRANS | \
262 EBC_BXAP_CSN_ENCODE(0) | \
263 EBC_BXAP_OEN_ENCODE(0) | \
264 EBC_BXAP_WBN_ENCODE(0) | \
265 EBC_BXAP_WBF_ENCODE(0) | \
266 EBC_BXAP_TH_ENCODE(0) | \
267 EBC_BXAP_RE_DISABLED | \
268 EBC_BXAP_SOR_NONDELAYED | \
269 EBC_BXAP_BEM_WRITEONLY | \
270 EBC_BXAP_PEN_DISABLED)
271 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
277 * Initialize EBC CONFIG -
278 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
279 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
281 #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
282 EBC_CFG_PTD_ENABLE | \
283 EBC_CFG_RTC_16PERCLK | \
284 EBC_CFG_ATC_PREVIOUS | \
285 EBC_CFG_DTC_PREVIOUS | \
286 EBC_CFG_CTC_PREVIOUS | \
287 EBC_CFG_OEO_PREVIOUS | \
288 EBC_CFG_EMC_DEFAULT | \
289 EBC_CFG_PME_DISABLE | \
295 #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
296 #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
297 #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
298 #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
300 #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
301 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
302 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
303 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
304 #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
305 #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
306 #define CONFIG_SYS_GPIO_ODR 0
308 #endif /* __CONFIG_H */