3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * SPDX-License-Identifier: GPL-2.0+
9 * Config header file for Hymod board
16 * High Level Configuration Options
20 #define CONFIG_HYMOD 1 /* ...on a Hymod board */
21 #define CONFIG_CPM2 1 /* Has a CPM2 */
23 #define CONFIG_SYS_TEXT_BASE 0x40000000
25 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
27 #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
30 * select serial console configuration
32 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
33 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
36 * if CONFIG_CONS_NONE is defined, then the serial console routines must
37 * defined elsewhere (for example, on the cogent platform, there are serial
38 * ports on the motherboard which are used for the serial console - see
39 * cogent/cma101/serial.[ch]).
41 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
42 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
43 #undef CONFIG_CONS_NONE /* define if console on something else*/
44 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
45 #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
46 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
47 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
50 * select ethernet configuration
52 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
53 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
56 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
57 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
59 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
60 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
61 #undef CONFIG_ETHER_NONE /* define if ether on something else */
62 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
63 #define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
65 #ifdef CONFIG_ETHER_ON_FCC
67 #if (CONFIG_ETHER_INDEX == 1)
72 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
73 * - Enable Full Duplex in FSMR
75 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
76 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
77 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
78 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
80 # define MDIO_PORT 0 /* Port A */
81 # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
82 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
83 # define MDC_DECLARE MDIO_DECLARE
85 # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
86 # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
88 #elif (CONFIG_ETHER_INDEX == 2)
93 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
94 * - Enable Full Duplex in FSMR
96 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
97 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
98 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
99 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
101 # define MDIO_PORT 0 /* Port A */
102 # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
103 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
104 # define MDC_DECLARE MDIO_DECLARE
106 # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
107 # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
109 #elif (CONFIG_ETHER_INDEX == 3)
114 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
115 * - Enable Full Duplex in FSMR
117 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
118 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
119 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
120 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
122 # define MDIO_PORT 0 /* Port A */
123 # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
124 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
125 # define MDC_DECLARE MDIO_DECLARE
127 # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
128 # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
130 #endif /* CONFIG_ETHER_INDEX */
132 #define CONFIG_MII /* MII PHY management */
133 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
135 #define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
136 #define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
137 #define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
139 #define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
140 else iop->pdat &= ~MDIO_DATA_PINMASK
142 #define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
143 else iop->pdat &= ~MDIO_CLCK_PINMASK
145 #define MIIDELAY udelay(1)
147 #endif /* CONFIG_ETHER_ON_FCC */
151 #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
152 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
154 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
156 #define CONFIG_8260_CLKIN 33333333 /* in Hz */
158 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
161 #if defined(CONFIG_CONS_USE_EXTC)
162 #define CONFIG_BAUDRATE 115200
164 #define CONFIG_BAUDRATE 9600
167 /* default ip addresses - these will be overridden */
168 #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
169 #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
171 #define CONFIG_LAST_STAGE_INIT
176 #define CONFIG_BOOTP_BOOTFILESIZE
177 #define CONFIG_BOOTP_BOOTPATH
178 #define CONFIG_BOOTP_GATEWAY
179 #define CONFIG_BOOTP_HOSTNAME
183 * Command line configuration.
185 #include <config_cmd_default.h>
187 #define CONFIG_CMD_ASKENV
188 #define CONFIG_CMD_BSP
189 #define CONFIG_CMD_CACHE
190 #define CONFIG_CMD_CDP
191 #define CONFIG_CMD_DATE
192 #define CONFIG_CMD_DHCP
193 #define CONFIG_CMD_DIAG
194 #define CONFIG_CMD_DTT
195 #define CONFIG_CMD_EEPROM
196 #define CONFIG_CMD_ELF
197 #define CONFIG_CMD_FAT
198 #define CONFIG_CMD_I2C
199 #define CONFIG_CMD_IMMAP
200 #define CONFIG_CMD_IRQ
201 #define CONFIG_CMD_KGDB
202 #define CONFIG_CMD_MII
203 #define CONFIG_CMD_PING
204 #define CONFIG_CMD_PORTIO
205 #define CONFIG_CMD_REGINFO
206 #define CONFIG_CMD_SAVES
207 #define CONFIG_CMD_SDRAM
208 #define CONFIG_CMD_SNTP
210 #undef CONFIG_CMD_FPGA
211 #undef CONFIG_CMD_XIMG
214 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
216 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
217 #define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
218 #define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
219 /* Be selective on what keys can delay or stop the autoboot process
222 #define CONFIG_AUTOBOOT_KEYED
223 #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
224 "press <SPACE> to stop\n", bootdelay
225 #define CONFIG_AUTOBOOT_STOP_STR " "
226 #undef CONFIG_AUTOBOOT_DELAY_STR
227 #define DEBUG_BOOTKEYS 0
230 #if defined(CONFIG_CMD_KGDB)
231 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
232 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
233 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
234 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
235 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
236 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
237 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
238 # if defined(CONFIG_KGDB_USE_EXTC)
239 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
241 #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
245 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
247 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
250 * Hymod specific configurable options
252 #undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */
255 * Miscellaneous configurable options
257 #define CONFIG_SYS_LONGHELP /* undef to save memory */
258 #if defined(CONFIG_CMD_KGDB)
259 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
261 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
263 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
264 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
265 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
267 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
268 #define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
270 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
272 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
274 #define CONFIG_SYS_I2C_SPEED 50000
275 #define CONFIG_SYS_I2C_SLAVE 0x7e
277 /* these are for the ST M24C02 2kbit serial i2c eeprom */
278 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
279 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
280 /* mask of address bits that overflow into the "EEPROM chip address" */
281 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
284 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
286 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
288 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
291 * standard dtt sensor configuration - bottom bit will determine local or
292 * remote sensor of the ADM1021, the rest determines index into
293 * CONFIG_SYS_DTT_ADM1021 array below.
295 * On HYMOD board, the remote sensor should be connected to the MPC8260
296 * temperature diode thingy, but an errata said this didn't work and
297 * should be disabled - so it isn't connected.
300 #define CONFIG_DTT_SENSORS { 0, 1 }
302 #define CONFIG_DTT_SENSORS { 0 }
306 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
307 * there will be one entry in this array for each two (dummy) sensors in
308 * CONFIG_DTT_SENSORS.
312 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
313 * - conversion rate 0x02 = 0.25 conversions/second
314 * - ALERT ouput disabled
315 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
316 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
318 #define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
321 * Low Level Configuration Settings
322 * (address mappings, register initial values, etc.)
323 * You should know what you are doing if you make changes here.
326 /*-----------------------------------------------------------------------
327 * Hard Reset Configuration Words
329 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
330 * defines for the various registers affected by the HRCW e.g. changing
331 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
334 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
335 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
338 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
339 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
342 /* no slaves so just duplicate the master hrcw */
343 #define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
344 #define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
345 #define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
346 #define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
347 #define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
348 #define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
349 #define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
351 /*-----------------------------------------------------------------------
352 * Internal Memory Mapped Register
354 #define CONFIG_SYS_IMMR 0xF0000000
356 /*-----------------------------------------------------------------------
357 * Definitions for initial stack pointer and data area (in DPRAM)
359 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
360 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
361 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
362 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
364 /*-----------------------------------------------------------------------
365 * Start addresses for the final memory configuration
366 * (Set up by the startup code)
367 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
369 #define CONFIG_SYS_SDRAM_BASE 0x00000000
370 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
371 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
372 #define CONFIG_SYS_FPGA_BASE 0x80000000
374 * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
375 * (very large i.e. 256kB) environment flash sector
377 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
378 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
381 * For booting Linux, the board info and command line data
382 * have to be in the first 8 MB of memory, since this is
383 * the maximum mapped by the Linux kernel during initialization.
385 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
387 /*-----------------------------------------------------------------------
390 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
391 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
393 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
394 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
396 #define CONFIG_ENV_IS_IN_FLASH 1
397 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
398 #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
399 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
400 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
402 /*-----------------------------------------------------------------------
403 * Cache Configuration
405 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
406 #if defined(CONFIG_CMD_KGDB)
407 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
410 /*-----------------------------------------------------------------------
411 * HIDx - Hardware Implementation-dependent Registers 2-11
412 *-----------------------------------------------------------------------
413 * HID0 also contains cache control - initially enable both caches and
414 * invalidate contents, then the final state leaves only the instruction
415 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
416 * but Soft reset does not.
418 * HID1 has only read-only information - nothing to set.
420 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
423 #define CONFIG_SYS_HID0_FINAL 0
425 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
427 #define CONFIG_SYS_HID2 0
429 /*-----------------------------------------------------------------------
430 * RMR - Reset Mode Register 5-5
431 *-----------------------------------------------------------------------
432 * turn on Checkstop Reset Enable
435 #define CONFIG_SYS_RMR 0
437 #define CONFIG_SYS_RMR RMR_CSRE
440 /*-----------------------------------------------------------------------
441 * BCR - Bus Configuration 4-25
442 *-----------------------------------------------------------------------
444 #define CONFIG_SYS_BCR (BCR_ETM)
446 /*-----------------------------------------------------------------------
447 * SIUMCR - SIU Module Configuration 4-31
448 *-----------------------------------------------------------------------
450 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
451 SIUMCR_APPC10|SIUMCR_MMR11)
453 /*-----------------------------------------------------------------------
454 * SYPCR - System Protection Control 4-35
455 * SYPCR can only be written once after reset!
456 *-----------------------------------------------------------------------
457 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
459 #if defined(CONFIG_WATCHDOG)
460 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
461 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
463 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
464 SYPCR_SWRI|SYPCR_SWP)
465 #endif /* CONFIG_WATCHDOG */
467 /*-----------------------------------------------------------------------
468 * TMCNTSC - Time Counter Status and Control 4-40
469 *-----------------------------------------------------------------------
470 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
471 * and enable Time Counter
473 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
475 /*-----------------------------------------------------------------------
476 * PISCR - Periodic Interrupt Status and Control 4-42
477 *-----------------------------------------------------------------------
478 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
481 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
483 /*-----------------------------------------------------------------------
484 * SCCR - System Clock Control 9-8
485 *-----------------------------------------------------------------------
486 * Ensure DFBRG is Divide by 16
488 #define CONFIG_SYS_SCCR (SCCR_DFBRG01)
490 /*-----------------------------------------------------------------------
491 * RCCR - RISC Controller Configuration 13-7
492 *-----------------------------------------------------------------------
494 #define CONFIG_SYS_RCCR 0
497 * Init Memory Controller:
499 * Bank Bus Machine PortSz Device
500 * ---- --- ------- ------ ------
501 * 0 60x GPCM 32 bit FLASH
502 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
503 * 2 60x SDRAM 64 bit SDRAM
504 * 3 Local UPMC 8 bit Main Xilinx configuration
505 * 4 Local GPCM 32 bit Main Xilinx register mode
506 * 5 Local UPMB 32 bit Main Xilinx port mode
507 * 6 Local UPMC 8 bit Mezz Xilinx configuration
513 * Quotes from the HYMOD IO Board Reference manual:
515 * "The flash memory is two Intel StrataFlash chips, each configured for
516 * 16 bit operation and connected to give a 32 bit wide port."
518 * "The chip select logic is configured to respond to both *CS0 and *CS1.
519 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
520 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
521 * FLASH will then appear as ROM during boot."
523 * Initially, we are only going to use bank 0 in read/write mode.
526 /* 32 bit, read-write, GPCM on 60x bus */
527 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
528 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
530 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
535 * Quotes from the HYMOD IO Board Reference manual:
537 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
538 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
539 * dynamic random access memory organised as 4 banks by 4096 rows by 512
540 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
542 * "The locations in SDRAM are accessed using multiplexed address pins to
543 * specify row and column. The pins also act to specify commands. The state
544 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
545 * pin may function as a row address or as the AUTO PRECHARGE control line,
546 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
547 * address lines to be configured to the required multiplexing scheme."
550 #define CONFIG_SYS_SDRAM_SIZE 64
552 /* 64 bit, read-write, SDRAM on 60x bus */
553 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
554 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
555 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
556 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
557 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
560 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
562 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
563 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
564 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
565 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
566 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
567 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
568 * command is 2 clocks, earliest timing for PRECHARGE after last data
569 * was read is 1 clock, earliest timing for PRECHARGE after last data
570 * was written is 1 clock, CAS Latency is 2.
573 #define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
574 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
575 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
576 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
577 PSDMR_WRC_1C|PSDMR_CL_2)
580 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
581 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
582 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
583 * Prescaler, hence the P instead of the R). The refresh timer period is given
584 * by (note that there was a change in the 8260 UM Errata):
586 * TimerPeriod = (PSRT + 1) / Fmptc
588 * where Fmptc is the BusClock divided by PTP. i.e.
590 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
594 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
596 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
597 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
600 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
601 * appear to be reasonable.
605 #define CONFIG_SYS_PSRT 39
606 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
608 #define CONFIG_SYS_PSRT 31
609 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
613 * Banks 3,4,5 and 6 - FPGA access
615 * Quotes from the HYMOD IO Board Reference manual:
617 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
618 * for configuring an optional FPGA on the mezzanine interface.
620 * Access to the FPGAs may be divided into several catagories:
623 * 2. Register mode access
624 * 3. Port mode access
626 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
627 * configured only (mode 1). Consequently there are four access types.
629 * To improve interface performance and simplify software design, the four
630 * possible access types are separately mapped to different memory banks.
632 * All are accessed using the local bus."
634 * Device Mode Memory Bank Machine Port Size Access
636 * Main Configuration 3 UPMC 8bit R/W
637 * Main Register 4 GPCM 32bit R/W
638 * Main Port 5 UPMB 32bit R/W
639 * Mezzanine Configuration 6 UPMC 8bit W/O
641 * "Note that mezzanine mode 1 access is write-only."
644 /* all the bank sizes must be a power of two, greater or equal to 32768 */
645 #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE)
646 #define FPGA_MAIN_CFG_SIZE 32768
647 #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
648 #define FPGA_MAIN_REG_SIZE 32768
649 #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
650 #define FPGA_MAIN_PORT_SIZE 32768
651 #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
652 #define FPGA_MEZZ_CFG_SIZE 32768
654 /* 8 bit, read-write, UPMC */
655 #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
656 /* up to 32Kbyte, burst inhibit */
657 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
659 /* 32 bit, read-write, GPCM */
660 #define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
662 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
664 /* 32 bit, read-write, UPMB */
665 #define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
667 #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
669 /* 8 bit, write-only, UPMC */
670 #define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
671 /* up to 32Kbyte, burst inhibit */
672 #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
674 /*-----------------------------------------------------------------------
675 * MBMR - Machine B Mode 10-27
676 *-----------------------------------------------------------------------
678 #define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
680 /*-----------------------------------------------------------------------
681 * MCMR - Machine C Mode 10-27
682 *-----------------------------------------------------------------------
684 #define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
687 * FPGA I/O Port/Bit information
690 #define FPGA_MAIN_PROG_PORT IOPIN_PORTA
691 #define FPGA_MAIN_PROG_PIN 4 /* PA4 */
692 #define FPGA_MAIN_INIT_PORT IOPIN_PORTA
693 #define FPGA_MAIN_INIT_PIN 5 /* PA5 */
694 #define FPGA_MAIN_DONE_PORT IOPIN_PORTA
695 #define FPGA_MAIN_DONE_PIN 6 /* PA6 */
697 #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
698 #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
699 #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
700 #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
701 #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
702 #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
703 #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
704 #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
707 * FPGA Interrupt configuration
709 #define FPGA_MAIN_IRQ SIU_INT_IRQ2
715 /* No command line, one static partition, whole device */
716 #undef CONFIG_CMD_MTDPARTS
717 #define CONFIG_JFFS2_DEV "nor0"
718 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
719 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
721 /* mtdparts command line support */
723 #define CONFIG_CMD_MTDPARTS
724 #define MTDIDS_DEFAULT ""
725 #define MTDPARTS_DEFAULT ""
728 #endif /* __CONFIG_H */