2 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_HSDK_H_
8 #define _CONFIG_HSDK_H_
10 #include <linux/sizes.h>
16 #define ARC_PERIPHERAL_BASE 0xF0000000
17 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
21 * Memory configuration
23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
25 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
26 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
29 #define CONFIG_SYS_INIT_SP_ADDR \
30 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
32 #define CONFIG_SYS_MALLOC_LEN SZ_2M
33 #define CONFIG_SYS_BOOTM_LEN SZ_128M
34 #define CONFIG_SYS_LOAD_ADDR 0x82000000
37 * This board might be of different versions so handle it
39 #define CONFIG_BOARD_TYPES
44 #define CONFIG_DW_SERIAL
45 #define CONFIG_SYS_NS16550_SERIAL
46 #define CONFIG_SYS_NS16550_CLK 33330000
47 #define CONFIG_SYS_NS16550_MEM32
50 * Ethernet PHY configuration
55 * USB 1.1 configuration
57 #define CONFIG_USB_OHCI_NEW
58 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
61 * Environment settings
63 #define CONFIG_ENV_SIZE SZ_16K
65 #define CONFIG_EXTRA_ENV_SETTINGS \
66 "core_dccm_0=0x10\0" \
68 "core_dccm_2=0x10\0" \
70 "core_iccm_0=0x10\0" \
72 "core_iccm_2=0x10\0" \
77 "non_volatile_limit=0xE\0" \
78 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
79 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
80 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
81 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
82 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
83 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
84 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
85 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
86 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
87 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
88 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
89 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
90 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
91 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
92 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
93 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
94 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
95 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
96 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
97 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
98 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
99 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
100 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
101 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
102 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
103 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
104 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
105 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
106 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
107 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
110 * Environment configuration
112 #define CONFIG_BOOTFILE "uImage"
113 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
116 * Misc utility configuration
118 #define CONFIG_BOUNCE_BUFFER
120 /* Cli configuration */
121 #define CONFIG_SYS_CBSIZE SZ_2K
124 * Callback configuration
126 #define CONFIG_BOARD_LATE_INIT
128 #endif /* _CONFIG_HSDK_H_ */