1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
6 #ifndef _CONFIG_HSDK_H_
7 #define _CONFIG_HSDK_H_
9 #include <linux/sizes.h>
15 #define ARC_PERIPHERAL_BASE 0xF0000000
16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
20 * Memory configuration
22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
28 #define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
31 #define CONFIG_SYS_MALLOC_LEN SZ_2M
32 #define CONFIG_SYS_BOOTM_LEN SZ_128M
33 #define CONFIG_SYS_LOAD_ADDR 0x82000000
36 * This board might be of different versions so handle it
38 #define CONFIG_BOARD_TYPES
43 #define CONFIG_DW_SERIAL
44 #define CONFIG_SYS_NS16550_SERIAL
45 #define CONFIG_SYS_NS16550_CLK 33330000
46 #define CONFIG_SYS_NS16550_MEM32
49 * Ethernet PHY configuration
54 * USB 1.1 configuration
56 #define CONFIG_USB_OHCI_NEW
57 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
60 * Environment settings
62 #define CONFIG_ENV_SIZE SZ_16K
64 #define CONFIG_EXTRA_ENV_SETTINGS \
65 "core_dccm_0=0x10\0" \
67 "core_dccm_2=0x10\0" \
69 "core_iccm_0=0x10\0" \
71 "core_iccm_2=0x10\0" \
76 "non_volatile_limit=0xE\0" \
77 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
78 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
79 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
80 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
81 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
82 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
83 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
84 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
85 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
86 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
87 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
88 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
89 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
90 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
91 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
92 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
93 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
94 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
95 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
96 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
97 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
98 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
99 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
100 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
101 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
102 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
103 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
104 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
105 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
106 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
109 * Environment configuration
111 #define CONFIG_BOOTFILE "uImage"
112 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
115 * Misc utility configuration
117 #define CONFIG_BOUNCE_BUFFER
119 /* Cli configuration */
120 #define CONFIG_SYS_CBSIZE SZ_2K
123 * Callback configuration
125 #define CONFIG_BOARD_LATE_INIT
127 #endif /* _CONFIG_HSDK_H_ */