1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
6 #ifndef _CONFIG_HSDK_H_
7 #define _CONFIG_HSDK_H_
9 #include <linux/sizes.h>
15 #define ARC_PERIPHERAL_BASE 0xF0000000
16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
20 * Memory configuration
22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
28 #define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
31 #define CONFIG_SYS_MALLOC_LEN SZ_2M
32 #define CONFIG_SYS_BOOTM_LEN SZ_128M
33 #define CONFIG_SYS_LOAD_ADDR 0x82000000
36 * This board might be of different versions so handle it
38 #define CONFIG_BOARD_TYPES
43 #define CONFIG_SYS_NS16550_SERIAL
44 #define CONFIG_SYS_NS16550_CLK 33330000
45 #define CONFIG_SYS_NS16550_MEM32
48 * Ethernet PHY configuration
52 * USB 1.1 configuration
54 #define CONFIG_USB_OHCI_NEW
55 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
58 * Environment settings
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "upgrade=if mmc rescan && " \
62 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
63 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
64 "\"Fail to upgrade.\n" \
65 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
67 "core_dccm_0=0x10\0" \
69 "core_dccm_2=0x10\0" \
71 "core_iccm_0=0x10\0" \
73 "core_iccm_2=0x10\0" \
78 "non_volatile_limit=0xE\0" \
79 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
80 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
81 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
82 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
83 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
84 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
85 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
86 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
87 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
88 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
89 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
90 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
91 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
92 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
93 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
94 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
95 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
96 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
97 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
98 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
99 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
100 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
101 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
102 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
103 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
104 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
105 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
106 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
107 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
108 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
111 * Environment configuration
113 #define CONFIG_BOOTFILE "uImage"
114 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
116 /* Cli configuration */
117 #define CONFIG_SYS_CBSIZE SZ_2K
120 * Callback configuration
122 #define CONFIG_BOARD_LATE_INIT
124 #endif /* _CONFIG_HSDK_H_ */