1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
6 #ifndef _CONFIG_HSDK_H_
7 #define _CONFIG_HSDK_H_
9 #include <linux/sizes.h>
15 #define ARC_PERIPHERAL_BASE 0xF0000000
16 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
17 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
20 * Memory configuration
23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
25 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
27 #define CONFIG_SYS_BOOTM_LEN SZ_128M
32 #define CONFIG_SYS_NS16550_SERIAL
33 #define CONFIG_SYS_NS16550_CLK 33330000
34 #define CONFIG_SYS_NS16550_MEM32
37 * Ethernet PHY configuration
41 * USB 1.1 configuration
43 #define CONFIG_USB_OHCI_NEW
44 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
47 * Environment settings
49 #define CONFIG_EXTRA_ENV_SETTINGS \
50 "upgrade=if mmc rescan && " \
51 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
52 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
53 "\"Fail to upgrade.\n" \
54 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
56 "core_dccm_0=0x10\0" \
58 "core_dccm_2=0x10\0" \
60 "core_iccm_0=0x10\0" \
62 "core_iccm_2=0x10\0" \
67 "non_volatile_limit=0xE\0" \
68 "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
69 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
70 setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
71 "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
72 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
73 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
74 "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
75 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
76 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
77 "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
78 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
79 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
80 "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
81 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
82 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
83 "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
84 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
85 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
86 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
87 "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
88 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
89 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
90 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
91 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
92 "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
93 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
94 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
95 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
96 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
97 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
99 /* Cli configuration */
102 * Callback configuration
105 #endif /* _CONFIG_HSDK_H_ */