1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
7 #ifndef _CONFIG_HSDK_H_
8 #define _CONFIG_HSDK_H_
10 #include <linux/sizes.h>
16 #define ARC_PERIPHERAL_BASE 0xF0000000
17 #define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18 #define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
21 * Memory configuration
24 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_SDRAM_SIZE SZ_1G
31 #define CONFIG_SYS_NS16550_SERIAL
32 #define CONFIG_SYS_NS16550_CLK 33330000
33 #define CONFIG_SYS_NS16550_MEM32
36 * Ethernet PHY configuration
40 * Environment settings
42 #define CONFIG_EXTRA_ENV_SETTINGS \
43 "upgrade=if mmc rescan && " \
44 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
45 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
46 "\"Fail to upgrade.\n" \
47 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
50 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
51 setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
52 setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
53 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
54 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
55 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
56 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
57 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
58 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
59 setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
60 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
61 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
62 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
63 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
64 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
65 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
66 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
67 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
68 setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
69 setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
70 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
71 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
72 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
73 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
74 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
75 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
76 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
77 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
78 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
79 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
80 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
81 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
82 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
83 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
84 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
85 setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
86 setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
87 setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
88 setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
89 setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
90 setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
93 * Environment configuration
96 /* Cli configuration */
99 * Callback configuration
102 #endif /* _CONFIG_HSDK_H_ */