include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  16
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18
  19 /*
  20  * Hardware Reset Configuration Word
  21  * if CLKIN is 66.66MHz, then
  22  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  23  * We choose the A type silicon as default, so the core is 400Mhz.
  24  */
  25 #define CONFIG_SYS_HRCW_LOW (\
  26         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  27         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  28         HRCWL_SVCOD_DIV_2 |\
  29         HRCWL_CSB_TO_CLKIN_4X1 |\
  30         HRCWL_CORE_TO_CSB_3X1)
  31 /*
  32  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  33  * in 8308's HRCWH according to the manual, but original Freescale's
  34  * code has them and I've expirienced some problems using the board
  35  * with BDI3000 attached when I've tried to set these bits to zero
  36  * (UART doesn't work after the 'reset run' command).
  37  */
  38 #define CONFIG_SYS_HRCW_HIGH (\
  39         HRCWH_PCI_HOST |\
  40         HRCWH_PCI1_ARBITER_ENABLE |\
  41         HRCWH_CORE_ENABLE |\
  42         HRCWH_FROM_0XFFF00100 |\
  43         HRCWH_BOOTSEQ_DISABLE |\
  44         HRCWH_SW_WATCHDOG_DISABLE |\
  45         HRCWH_ROM_LOC_LOCAL_16BIT |\
  46         HRCWH_RL_EXT_LEGACY |\
  47         HRCWH_TSEC1M_IN_RGMII |\
  48         HRCWH_TSEC2M_IN_RGMII |\
  49         HRCWH_BIG_ENDIAN)
  50
  51 /*
  52  * System IO Config
  53  */
  54 #define CONFIG_SYS_SICRH (\
  55         SICRH_ESDHC_A_SD |\
  56         SICRH_ESDHC_B_SD |\
  57         SICRH_ESDHC_C_SD |\
  58         SICRH_GPIO_A_GPIO |\
  59         SICRH_GPIO_B_GPIO |\
  60         SICRH_IEEE1588_A_GPIO |\
  61         SICRH_USB |\
  62         SICRH_GTM_GPIO |\
  63         SICRH_IEEE1588_B_GPIO |\
  64         SICRH_ETSEC2_GPIO |\
  65         SICRH_GPIOSEL_1 |\
  66         SICRH_TMROBI_V3P3 |\
  67         SICRH_TSOBI1_V2P5 |\
  68         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  69 #define CONFIG_SYS_SICRL (\
  70         SICRL_SPI_PF0 |\
  71         SICRL_UART_PF0 |\
  72         SICRL_IRQ_PF0 |\
  73         SICRL_I2C2_PF0 |\
  74         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CONFIG_SYS_IMMR         0xE0000000
  80
  81 /*
  82  * SERDES
  83  */
  84 #define CONFIG_FSL_SERDES
  85 #define CONFIG_FSL_SERDES1      0xe3000
  86
  87 /*
  88  * Arbiter Setup
  89  */
  90 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  91 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  92 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  93
  94 /*
  95  * DDR Setup
  96  */
  97 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  98 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  99 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 100 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 101 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 102                                 | DDRCDR_PZ_LOZ \
 103                                 | DDRCDR_NZ_LOZ \
 104                                 | DDRCDR_ODT \
 105                                 | DDRCDR_Q_DRN)
 106                                 /* 0x7b880001 */
 107 /*
 108  * Manually set up DDR parameters
 109  * consist of one chip NT5TU64M16HG from NANYA
 110  */
 111
 112 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 113
 114 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 115 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 116                                 | CSCONFIG_ODT_RD_NEVER \
 117                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 118                                 | CSCONFIG_BANK_BIT_3 \
 119                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 120                                 /* 0x80010102 */
 121 #define CONFIG_SYS_DDR_TIMING_3 0
 122 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 123                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 124                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 125                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 126                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 127                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 128                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 129                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 130                                 /* 0x00260802 */
 131 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 132                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 133                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 134                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 135                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 136                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 137                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 138                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 139                                 /* 0x26279222 */
 140 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 141                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 142                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 143                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 144                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 145                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 146                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 147                                 /* 0x021848c5 */
 148 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 149                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 150                                 /* 0x08240100 */
 151 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 152                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 153                                 | SDRAM_CFG_DBW_16)
 154                                 /* 0x43100000 */
 155
 156 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 157 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 158                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 159                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 160 #define CONFIG_SYS_DDR_MODE2            0x00000000
 161
 162 /*
 163  * Memory test
 164  */
 165 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 166 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 167
 168 /*
 169  * The reserved memory
 170  */
 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 172
 173 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 175
 176 /*
 177  * Initial RAM Base Address Setup
 178  */
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 183         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184
 185 /*
 186  * Local Bus Configuration & Clock Setup
 187  */
 188 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 189 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 190 #define CONFIG_SYS_LBC_LBCR             0x00040000
 191
 192 /*
 193  * FLASH on the Local Bus
 194  */
 195 #if 1
 196 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 197 #define CONFIG_FLASH_CFI_LEGACY
 198 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 199 #endif
 200
 201 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 202 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 203
 204 /* Window base at flash base */
 205 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 206 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 207
 208 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 209                                 | BR_PS_16      /* 16 bit port */ \
 210                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 211                                 | BR_V)         /* valid */
 212 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 213                                 | OR_UPM_XAM \
 214                                 | OR_GPCM_CSNT \
 215                                 | OR_GPCM_ACS_DIV2 \
 216                                 | OR_GPCM_XACS \
 217                                 | OR_GPCM_SCY_15 \
 218                                 | OR_GPCM_TRLX_SET \
 219                                 | OR_GPCM_EHTR_SET)
 220
 221 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 222 #define CONFIG_SYS_MAX_FLASH_SECT       135
 223
 224 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 225 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 226
 227 /*
 228  * FPGA
 229  */
 230 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 231 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 232
 233 /* Window base at FPGA base */
 234 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 235 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 236
 237 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 238                                 | BR_PS_16      /* 16 bit port */ \
 239                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 240                                 | BR_V)         /* valid */
 241 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 242                                 | OR_UPM_XAM \
 243                                 | OR_GPCM_CSNT \
 244                                 | OR_GPCM_ACS_DIV2 \
 245                                 | OR_GPCM_XACS \
 246                                 | OR_GPCM_SCY_15 \
 247                                 | OR_GPCM_TRLX_SET \
 248                                 | OR_GPCM_EHTR_SET)
 249
 250 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 251 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 252
 253 #define CONFIG_SYS_FPGA_COUNT           1
 254
 255 #define CONFIG_SYS_MCLINK_MAX           3
 256
 257 #define CONFIG_SYS_FPGA_PTR \
 258         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 259
 260 /*
 261  * Serial Port
 262  */
 263 #define CONFIG_SYS_NS16550_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE     1
 265 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 266
 267 #define CONFIG_SYS_BAUDRATE_TABLE  \
 268         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 269
 270 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 271 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 272
 273 /* Pass open firmware flat tree */
 274
 275 /* I2C */
 276 #define CONFIG_SYS_I2C
 277 #define CONFIG_SYS_I2C_FSL
 278 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 279 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 280 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 281
 282 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 283 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 284
 285 #define CONFIG_SYS_I2C_IHS
 286 #define CONFIG_SYS_I2C_IHS_CH0
 287 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 288 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 289 #define CONFIG_SYS_I2C_IHS_CH1
 290 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 291 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 292 #define CONFIG_SYS_I2C_IHS_CH2
 293 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 294 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 295 #define CONFIG_SYS_I2C_IHS_CH3
 296 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 297 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 298
 299 #ifdef CONFIG_HRCON_DH
 300 #define CONFIG_SYS_I2C_IHS_DUAL
 301 #define CONFIG_SYS_I2C_IHS_CH0_1
 302 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 303 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 304 #define CONFIG_SYS_I2C_IHS_CH1_1
 305 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 306 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 307 #define CONFIG_SYS_I2C_IHS_CH2_1
 308 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 309 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 310 #define CONFIG_SYS_I2C_IHS_CH3_1
 311 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 312 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 313 #endif
 314
 315 /*
 316  * Software (bit-bang) I2C driver configuration
 317  */
 318 #define CONFIG_SYS_I2C_SOFT
 319 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 320 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 321 #define I2C_SOFT_DECLARATIONS2
 322 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 323 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 324 #define I2C_SOFT_DECLARATIONS3
 325 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 326 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 327 #define I2C_SOFT_DECLARATIONS4
 328 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 329 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 330 #define I2C_SOFT_DECLARATIONS5
 331 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 332 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 333 #define I2C_SOFT_DECLARATIONS6
 334 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 335 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 336 #define I2C_SOFT_DECLARATIONS7
 337 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 338 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 339 #define I2C_SOFT_DECLARATIONS8
 340 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 341 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 342
 343 #ifdef CONFIG_HRCON_DH
 344 #define I2C_SOFT_DECLARATIONS9
 345 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 346 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 347 #define I2C_SOFT_DECLARATIONS10
 348 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 350 #define I2C_SOFT_DECLARATIONS11
 351 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 353 #define I2C_SOFT_DECLARATIONS12
 354 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 356 #endif
 357
 358 #ifdef CONFIG_HRCON_DH
 359 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 360 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 361 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 362                                                   {12, 0x4c} }
 363 #else
 364 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 365 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 366 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 367                                                   {8, 0x4c} }
 368 #endif
 369
 370 #ifndef __ASSEMBLY__
 371 void fpga_gpio_set(unsigned int bus, int pin);
 372 void fpga_gpio_clear(unsigned int bus, int pin);
 373 int fpga_gpio_get(unsigned int bus, int pin);
 374 void fpga_control_set(unsigned int bus, int pin);
 375 void fpga_control_clear(unsigned int bus, int pin);
 376 #endif
 377
 378 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 379 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 380 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 381
 382 #ifdef CONFIG_HRCON_DH
 383 #define I2C_ACTIVE \
 384         do { \
 385                 if (I2C_ADAP_HWNR > 7) \
 386                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 387                 else \
 388                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 389         } while (0)
 390 #else
 391 #define I2C_ACTIVE      { }
 392 #endif
 393 #define I2C_TRISTATE    { }
 394 #define I2C_READ \
 395         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 396 #define I2C_SDA(bit) \
 397         do { \
 398                 if (bit) \
 399                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 400                 else \
 401                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 402         } while (0)
 403 #define I2C_SCL(bit) \
 404         do { \
 405                 if (bit) \
 406                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 407                 else \
 408                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 409         } while (0)
 410 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 411
 412 /*
 413  * Software (bit-bang) MII driver configuration
 414  */
 415 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 416 #define CONFIG_BITBANGMII_MULTI
 417
 418 /*
 419  * OSD Setup
 420  */
 421 #define CONFIG_SYS_OSD_SCREENS          1
 422 #define CONFIG_SYS_DP501_DIFFERENTIAL
 423 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 424
 425 #ifdef CONFIG_HRCON_DH
 426 #define CONFIG_SYS_OSD_DH
 427 #endif
 428
 429 /*
 430  * General PCI
 431  * Addresses are mapped 1-1.
 432  */
 433 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 434 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 435 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 436 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 437 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 438 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 439 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 440 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 441 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 442
 443 /* enable PCIE clock */
 444 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 445
 446 #define CONFIG_PCI_INDIRECT_BRIDGE
 447 #define CONFIG_PCIE
 448
 449 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 450 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 451
 452 /*
 453  * TSEC
 454  */
 455 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 456 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 457
 458 /*
 459  * TSEC ethernet configuration
 460  */
 461 #define CONFIG_TSEC1
 462 #define CONFIG_TSEC1_NAME       "eTSEC0"
 463 #define TSEC1_PHY_ADDR          1
 464 #define TSEC1_PHYIDX            0
 465 #define TSEC1_FLAGS             TSEC_GIGABIT
 466
 467 /* Options are: eTSEC[0-1] */
 468 #define CONFIG_ETHPRIME         "eTSEC0"
 469
 470 /*
 471  * Environment
 472  */
 473 #if 1
 474 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 475                                  CONFIG_SYS_MONITOR_LEN)
 476 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 477 #define CONFIG_ENV_SIZE         0x2000
 478 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 479 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 480 #else
 481 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 482 #endif
 483
 484 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 485 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 486
 487 /*
 488  * Command line configuration.
 489  */
 490
 491 /*
 492  * Miscellaneous configurable options
 493  */
 494 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 495 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 496
 497 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 498
 499 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 500
 501 /*
 502  * For booting Linux, the board info and command line data
 503  * have to be in the first 256 MB of memory, since this is
 504  * the maximum mapped by the Linux kernel during initialization.
 505  */
 506 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 507
 508 /*
 509  * Core HID Setup
 510  */
 511 #define CONFIG_SYS_HID0_INIT    0x000000000
 512 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 513                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 514                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 515 #define CONFIG_SYS_HID2         HID2_HBE
 516
 517 /*
 518  * MMU Setup
 519  */
 520
 521 /* DDR: cache cacheable */
 522 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 523                                         BATL_MEMCOHERENCE)
 524 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 525                                         BATU_VS | BATU_VP)
 526 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 527 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 528
 529 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 530 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 531                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 532 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 533                                         BATU_VP)
 534 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 535 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 536
 537 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 538 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 539                                         BATL_MEMCOHERENCE)
 540 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 541                                         BATU_VS | BATU_VP)
 542 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 543                                         BATL_CACHEINHIBIT | \
 544                                         BATL_GUARDEDSTORAGE)
 545 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 546
 547 /* Stack in dcache: cacheable, no memory coherence */
 548 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 549 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 550                                         BATU_VS | BATU_VP)
 551 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 552 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 553
 554 /*
 555  * Environment Configuration
 556  */
 557
 558 #define CONFIG_ENV_OVERWRITE
 559
 560 #if defined(CONFIG_TSEC_ENET)
 561 #define CONFIG_HAS_ETH0
 562 #endif
 563
 564 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 565
 566
 567 #define CONFIG_HOSTNAME         "hrcon"
 568 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 569 #define CONFIG_BOOTFILE         "uImage"
 570
 571 #define CONFIG_PREBOOT          /* enable preboot variable */
 572
 573 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 574         "netdev=eth0\0"                                                 \
 575         "consoledev=ttyS1\0"                                            \
 576         "u-boot=u-boot.bin\0"                                           \
 577         "kernel_addr=1000000\0"                                 \
 578         "fdt_addr=C00000\0"                                             \
 579         "fdtfile=hrcon.dtb\0"                           \
 580         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 581         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 582                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 583                 " +${filesize};cp.b ${fileaddr} "                       \
 584                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 585         "upd=run load update\0"                                         \
 586
 587 #define CONFIG_NFSBOOTCOMMAND                                           \
 588         "setenv bootargs root=/dev/nfs rw "                             \
 589         "nfsroot=$serverip:$rootpath "                                  \
 590         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 591         "console=$consoledev,$baudrate $othbootargs;"                   \
 592         "tftp ${kernel_addr} $bootfile;"                                \
 593         "tftp ${fdt_addr} $fdtfile;"                                    \
 594         "bootm ${kernel_addr} - ${fdt_addr}"
 595
 596 #define CONFIG_MMCBOOTCOMMAND                                           \
 597         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 598         "console=$consoledev,$baudrate $othbootargs;"                   \
 599         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 600         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 601         "bootm ${kernel_addr} - ${fdt_addr}"
 602
 603 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 604
 605 #endif  /* __CONFIG_H */