Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / hrcon.h
1 /*
2  * (C) Copyright 2014
3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
4  *
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1 /* E300 family */
16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
17 #define CONFIG_MPC830x          1 /* MPC830x family */
18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
19 #define CONFIG_HRCON            1 /* HRCON board specific */
20
21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
22
23 #define CONFIG_IDENT_STRING     " hrcon 0.01"
24
25 #define CONFIG_SYS_GENERIC_BOARD
26
27 #define CONFIG_BOARD_EARLY_INIT_F
28 #define CONFIG_BOARD_EARLY_INIT_R
29 #define CONFIG_LAST_STAGE_INIT
30
31 /* new uImage format support */
32 #define CONFIG_FIT                      1
33 #define CONFIG_FIT_VERBOSE              1
34
35 #define CONFIG_MMC
36 #define CONFIG_FSL_ESDHC
37 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
38 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
39
40 #define CONFIG_CMD_MMC
41 #define CONFIG_GENERIC_MMC
42 #define CONFIG_DOS_PARTITION
43 #define CONFIG_CMD_EXT2
44
45 #define CONFIG_CMD_FPGAD
46 #define CONFIG_CMD_IOLOOP
47
48 /*
49  * System Clock Setup
50  */
51 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
52 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
53
54 /*
55  * Hardware Reset Configuration Word
56  * if CLKIN is 66.66MHz, then
57  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
58  * We choose the A type silicon as default, so the core is 400Mhz.
59  */
60 #define CONFIG_SYS_HRCW_LOW (\
61         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
62         HRCWL_DDR_TO_SCB_CLK_2X1 |\
63         HRCWL_SVCOD_DIV_2 |\
64         HRCWL_CSB_TO_CLKIN_4X1 |\
65         HRCWL_CORE_TO_CSB_3X1)
66 /*
67  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
68  * in 8308's HRCWH according to the manual, but original Freescale's
69  * code has them and I've expirienced some problems using the board
70  * with BDI3000 attached when I've tried to set these bits to zero
71  * (UART doesn't work after the 'reset run' command).
72  */
73 #define CONFIG_SYS_HRCW_HIGH (\
74         HRCWH_PCI_HOST |\
75         HRCWH_PCI1_ARBITER_ENABLE |\
76         HRCWH_CORE_ENABLE |\
77         HRCWH_FROM_0XFFF00100 |\
78         HRCWH_BOOTSEQ_DISABLE |\
79         HRCWH_SW_WATCHDOG_DISABLE |\
80         HRCWH_ROM_LOC_LOCAL_16BIT |\
81         HRCWH_RL_EXT_LEGACY |\
82         HRCWH_TSEC1M_IN_RGMII |\
83         HRCWH_TSEC2M_IN_RGMII |\
84         HRCWH_BIG_ENDIAN)
85
86 /*
87  * System IO Config
88  */
89 #define CONFIG_SYS_SICRH (\
90         SICRH_ESDHC_A_SD |\
91         SICRH_ESDHC_B_SD |\
92         SICRH_ESDHC_C_SD |\
93         SICRH_GPIO_A_GPIO |\
94         SICRH_GPIO_B_GPIO |\
95         SICRH_IEEE1588_A_GPIO |\
96         SICRH_USB |\
97         SICRH_GTM_GPIO |\
98         SICRH_IEEE1588_B_GPIO |\
99         SICRH_ETSEC2_GPIO |\
100         SICRH_GPIOSEL_1 |\
101         SICRH_TMROBI_V3P3 |\
102         SICRH_TSOBI1_V2P5 |\
103         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
104 #define CONFIG_SYS_SICRL (\
105         SICRL_SPI_PF0 |\
106         SICRL_UART_PF0 |\
107         SICRL_IRQ_PF0 |\
108         SICRL_I2C2_PF0 |\
109         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
110
111 /*
112  * IMMR new address
113  */
114 #define CONFIG_SYS_IMMR         0xE0000000
115
116 /*
117  * SERDES
118  */
119 #define CONFIG_FSL_SERDES
120 #define CONFIG_FSL_SERDES1      0xe3000
121
122 /*
123  * Arbiter Setup
124  */
125 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
126 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
127 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
128
129 /*
130  * DDR Setup
131  */
132 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
133 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
134 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
135 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
136 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
137                                 | DDRCDR_PZ_LOZ \
138                                 | DDRCDR_NZ_LOZ \
139                                 | DDRCDR_ODT \
140                                 | DDRCDR_Q_DRN)
141                                 /* 0x7b880001 */
142 /*
143  * Manually set up DDR parameters
144  * consist of one chip NT5TU64M16HG from NANYA
145  */
146
147 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
148
149 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
150 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
151                                 | CSCONFIG_ODT_RD_NEVER \
152                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
153                                 | CSCONFIG_BANK_BIT_3 \
154                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
155                                 /* 0x80010102 */
156 #define CONFIG_SYS_DDR_TIMING_3 0
157 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
158                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
159                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
160                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
161                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
162                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
163                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
164                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
165                                 /* 0x00260802 */
166 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
167                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
168                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
169                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
170                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
171                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
172                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
173                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
174                                 /* 0x26279222 */
175 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
176                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
177                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
178                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
179                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
180                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
181                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
182                                 /* 0x021848c5 */
183 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
184                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
185                                 /* 0x08240100 */
186 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
187                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
188                                 | SDRAM_CFG_DBW_16)
189                                 /* 0x43100000 */
190
191 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
192 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
193                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
194                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
195 #define CONFIG_SYS_DDR_MODE2            0x00000000
196
197 /*
198  * Memory test
199  */
200 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
201 #define CONFIG_SYS_MEMTEST_END          0x07f00000
202
203 /*
204  * The reserved memory
205  */
206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
207
208 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
209 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
210
211 /*
212  * Initial RAM Base Address Setup
213  */
214 #define CONFIG_SYS_INIT_RAM_LOCK        1
215 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
216 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
217 #define CONFIG_SYS_GBL_DATA_OFFSET      \
218         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219
220 /*
221  * Local Bus Configuration & Clock Setup
222  */
223 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
224 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
225 #define CONFIG_SYS_LBC_LBCR             0x00040000
226
227 /*
228  * FLASH on the Local Bus
229  */
230 #if 1
231 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
232 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
233 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
234 #define CONFIG_FLASH_CFI_LEGACY
235 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
236 #else
237 #define CONFIG_SYS_NO_FLASH
238 #endif
239
240 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
241 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
242 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
243
244 /* Window base at flash base */
245 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
246 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
247
248 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
249                                 | BR_PS_16      /* 16 bit port */ \
250                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
251                                 | BR_V)         /* valid */
252 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
253                                 | OR_UPM_XAM \
254                                 | OR_GPCM_CSNT \
255                                 | OR_GPCM_ACS_DIV2 \
256                                 | OR_GPCM_XACS \
257                                 | OR_GPCM_SCY_15 \
258                                 | OR_GPCM_TRLX_SET \
259                                 | OR_GPCM_EHTR_SET)
260
261 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
262 #define CONFIG_SYS_MAX_FLASH_SECT       135
263
264 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
265 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
266
267 /*
268  * FPGA
269  */
270 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
271 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
272
273 /* Window base at FPGA base */
274 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
275 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
276
277 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
278                                 | BR_PS_16      /* 16 bit port */ \
279                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
280                                 | BR_V)         /* valid */
281 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
282                                 | OR_UPM_XAM \
283                                 | OR_GPCM_CSNT \
284                                 | OR_GPCM_ACS_DIV2 \
285                                 | OR_GPCM_XACS \
286                                 | OR_GPCM_SCY_15 \
287                                 | OR_GPCM_TRLX_SET \
288                                 | OR_GPCM_EHTR_SET)
289
290 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
291 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
292
293 #define CONFIG_SYS_FPGA_COUNT           1
294
295 #define CONFIG_SYS_MCLINK_MAX           3
296
297 #define CONFIG_SYS_FPGA_PTR \
298         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
299
300 /*
301  * Serial Port
302  */
303 #define CONFIG_CONS_INDEX       2
304 #define CONFIG_SYS_NS16550
305 #define CONFIG_SYS_NS16550_SERIAL
306 #define CONFIG_SYS_NS16550_REG_SIZE     1
307 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
308
309 #define CONFIG_SYS_BAUDRATE_TABLE  \
310         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311
312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
314
315 /* Use the HUSH parser */
316 #define CONFIG_SYS_HUSH_PARSER
317
318 /* Pass open firmware flat tree */
319 #define CONFIG_OF_LIBFDT                1
320 #define CONFIG_OF_BOARD_SETUP           1
321 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
322
323 /* I2C */
324 #define CONFIG_SYS_I2C
325 #define CONFIG_SYS_I2C_FSL
326 #define CONFIG_SYS_FSL_I2C_SPEED        400000
327 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
328 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
329
330 #define CONFIG_PCA953X                  /* NXP PCA9554 */
331 #define CONFIG_PCA9698                  /* NXP PCA9698 */
332
333 #define CONFIG_SYS_I2C_IHS
334 #define CONFIG_SYS_I2C_IHS_CH0
335 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
336 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
337 #define CONFIG_SYS_I2C_IHS_CH1
338 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
339 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
340 #define CONFIG_SYS_I2C_IHS_CH2
341 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
342 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
343 #define CONFIG_SYS_I2C_IHS_CH3
344 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
345 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
346
347 /*
348  * Software (bit-bang) I2C driver configuration
349  */
350 #define CONFIG_SYS_I2C_SOFT
351 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
352 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
353 #define I2C_SOFT_DECLARATIONS2
354 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
355 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
356 #define I2C_SOFT_DECLARATIONS3
357 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
358 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
359 #define I2C_SOFT_DECLARATIONS4
360 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
361 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
362
363 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
364 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
365 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
366
367 #ifndef __ASSEMBLY__
368 void fpga_gpio_set(unsigned int bus, int pin);
369 void fpga_gpio_clear(unsigned int bus, int pin);
370 int fpga_gpio_get(unsigned int bus, int pin);
371 #endif
372
373 #define I2C_ACTIVE      { }
374 #define I2C_TRISTATE    { }
375 #define I2C_READ \
376         (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
377 #define I2C_SDA(bit) \
378         do { \
379                 if (bit) \
380                         fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
381                 else \
382                         fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
383         } while (0)
384 #define I2C_SCL(bit) \
385         do { \
386                 if (bit) \
387                         fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
388                 else \
389                         fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
390         } while (0)
391 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
392
393 /*
394  * Software (bit-bang) MII driver configuration
395  */
396 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
397 #define CONFIG_BITBANGMII_MULTI
398
399 /*
400  * OSD Setup
401  */
402 #define CONFIG_SYS_OSD_SCREENS          1
403 #define CONFIG_SYS_DP501_DIFFERENTIAL
404 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
405
406 /*
407  * General PCI
408  * Addresses are mapped 1-1.
409  */
410 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
411 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
412 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
413 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
414 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
415 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
416 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
417 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
418 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
419
420 /* enable PCIE clock */
421 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
422
423 #define CONFIG_PCI
424 #define CONFIG_PCI_INDIRECT_BRIDGE
425 #define CONFIG_PCIE
426
427 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
428
429 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
430 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
431
432 /*
433  * TSEC
434  */
435 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
436 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
437 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
438
439 /*
440  * TSEC ethernet configuration
441  */
442 #define CONFIG_MII              1 /* MII PHY management */
443 #define CONFIG_TSEC1
444 #define CONFIG_TSEC1_NAME       "eTSEC0"
445 #define TSEC1_PHY_ADDR          1
446 #define TSEC1_PHYIDX            0
447 #define TSEC1_FLAGS             TSEC_GIGABIT
448
449 /* Options are: eTSEC[0-1] */
450 #define CONFIG_ETHPRIME         "eTSEC0"
451
452 /*
453  * Environment
454  */
455 #if 1
456 #define CONFIG_ENV_IS_IN_FLASH  1
457 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
458                                  CONFIG_SYS_MONITOR_LEN)
459 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
460 #define CONFIG_ENV_SIZE         0x2000
461 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
462 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
463 #else
464 #define CONFIG_ENV_IS_NOWHERE
465 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
466 #endif
467
468 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
469 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
470
471 /*
472  * Command line configuration.
473  */
474 #include <config_cmd_default.h>
475
476 #define CONFIG_CMD_I2C
477 #define CONFIG_CMD_MII
478 #define CONFIG_CMD_NET
479 #define CONFIG_CMD_PCI
480 #define CONFIG_CMD_PING
481
482 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
483 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
484
485 /*
486  * Miscellaneous configurable options
487  */
488 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
489 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
490 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
491 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
492
493 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
494 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
495 #define CONFIG_AUTOBOOT_STOP_STR " "
496
497 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
498
499 #define CONFIG_SYS_CONSOLE_INFO_QUIET
500
501 /* Print Buffer Size */
502 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
503 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
504 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
505
506 /*
507  * For booting Linux, the board info and command line data
508  * have to be in the first 256 MB of memory, since this is
509  * the maximum mapped by the Linux kernel during initialization.
510  */
511 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
512
513 /*
514  * Core HID Setup
515  */
516 #define CONFIG_SYS_HID0_INIT    0x000000000
517 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
518                                  HID0_ENABLE_INSTRUCTION_CACHE | \
519                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
520 #define CONFIG_SYS_HID2         HID2_HBE
521
522 /*
523  * MMU Setup
524  */
525
526 /* DDR: cache cacheable */
527 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
528                                         BATL_MEMCOHERENCE)
529 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
530                                         BATU_VS | BATU_VP)
531 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
532 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
533
534 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
535 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
536                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
537 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
538                                         BATU_VP)
539 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
540 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
541
542 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
543 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
544                                         BATL_MEMCOHERENCE)
545 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
546                                         BATU_VS | BATU_VP)
547 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
548                                         BATL_CACHEINHIBIT | \
549                                         BATL_GUARDEDSTORAGE)
550 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
551
552 /* Stack in dcache: cacheable, no memory coherence */
553 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
554 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
555                                         BATU_VS | BATU_VP)
556 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
557 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
558
559 /*
560  * Environment Configuration
561  */
562
563 #define CONFIG_ENV_OVERWRITE
564
565 #if defined(CONFIG_TSEC_ENET)
566 #define CONFIG_HAS_ETH0
567 #endif
568
569 #define CONFIG_BAUDRATE 115200
570
571 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
572
573 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
574
575 #define CONFIG_HOSTNAME         hrcon
576 #define CONFIG_ROOTPATH         "/opt/nfsroot"
577 #define CONFIG_BOOTFILE         "uImage"
578
579 #define CONFIG_PREBOOT          /* enable preboot variable */
580
581 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
582         "netdev=eth0\0"                                                 \
583         "consoledev=ttyS1\0"                                            \
584         "u-boot=u-boot.bin\0"                                           \
585         "kernel_addr=1000000\0"                                 \
586         "fdt_addr=C00000\0"                                             \
587         "fdtfile=hrcon.dtb\0"                           \
588         "load=tftp ${loadaddr} ${u-boot}\0"                             \
589         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
590                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
591                 " +${filesize};cp.b ${fileaddr} "                       \
592                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
593         "upd=run load update\0"                                         \
594
595 #define CONFIG_NFSBOOTCOMMAND                                           \
596         "setenv bootargs root=/dev/nfs rw "                             \
597         "nfsroot=$serverip:$rootpath "                                  \
598         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
599         "console=$consoledev,$baudrate $othbootargs;"                   \
600         "tftp ${kernel_addr} $bootfile;"                                \
601         "tftp ${fdt_addr} $fdtfile;"                                    \
602         "bootm ${kernel_addr} - ${fdt_addr}"
603
604 #define CONFIG_MMCBOOTCOMMAND                                           \
605         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
606         "console=$consoledev,$baudrate $othbootargs;"                   \
607         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
608         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
609         "bootm ${kernel_addr} - ${fdt_addr}"
610
611 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
612
613
614 #endif  /* __CONFIG_H */