include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  16
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18
  19 /*
  20  * System Clock Setup
  21  */
  22 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  23 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  24
  25 /*
  26  * Hardware Reset Configuration Word
  27  * if CLKIN is 66.66MHz, then
  28  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  29  * We choose the A type silicon as default, so the core is 400Mhz.
  30  */
  31 #define CONFIG_SYS_HRCW_LOW (\
  32         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  33         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  34         HRCWL_SVCOD_DIV_2 |\
  35         HRCWL_CSB_TO_CLKIN_4X1 |\
  36         HRCWL_CORE_TO_CSB_3X1)
  37 /*
  38  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  39  * in 8308's HRCWH according to the manual, but original Freescale's
  40  * code has them and I've expirienced some problems using the board
  41  * with BDI3000 attached when I've tried to set these bits to zero
  42  * (UART doesn't work after the 'reset run' command).
  43  */
  44 #define CONFIG_SYS_HRCW_HIGH (\
  45         HRCWH_PCI_HOST |\
  46         HRCWH_PCI1_ARBITER_ENABLE |\
  47         HRCWH_CORE_ENABLE |\
  48         HRCWH_FROM_0XFFF00100 |\
  49         HRCWH_BOOTSEQ_DISABLE |\
  50         HRCWH_SW_WATCHDOG_DISABLE |\
  51         HRCWH_ROM_LOC_LOCAL_16BIT |\
  52         HRCWH_RL_EXT_LEGACY |\
  53         HRCWH_TSEC1M_IN_RGMII |\
  54         HRCWH_TSEC2M_IN_RGMII |\
  55         HRCWH_BIG_ENDIAN)
  56
  57 /*
  58  * System IO Config
  59  */
  60 #define CONFIG_SYS_SICRH (\
  61         SICRH_ESDHC_A_SD |\
  62         SICRH_ESDHC_B_SD |\
  63         SICRH_ESDHC_C_SD |\
  64         SICRH_GPIO_A_GPIO |\
  65         SICRH_GPIO_B_GPIO |\
  66         SICRH_IEEE1588_A_GPIO |\
  67         SICRH_USB |\
  68         SICRH_GTM_GPIO |\
  69         SICRH_IEEE1588_B_GPIO |\
  70         SICRH_ETSEC2_GPIO |\
  71         SICRH_GPIOSEL_1 |\
  72         SICRH_TMROBI_V3P3 |\
  73         SICRH_TSOBI1_V2P5 |\
  74         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  75 #define CONFIG_SYS_SICRL (\
  76         SICRL_SPI_PF0 |\
  77         SICRL_UART_PF0 |\
  78         SICRL_IRQ_PF0 |\
  79         SICRL_I2C2_PF0 |\
  80         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  81
  82 /*
  83  * IMMR new address
  84  */
  85 #define CONFIG_SYS_IMMR         0xE0000000
  86
  87 /*
  88  * SERDES
  89  */
  90 #define CONFIG_FSL_SERDES
  91 #define CONFIG_FSL_SERDES1      0xe3000
  92
  93 /*
  94  * Arbiter Setup
  95  */
  96 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  97 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  98 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  99
 100 /*
 101  * DDR Setup
 102  */
 103 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 104 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 105 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 106 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 107 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 108                                 | DDRCDR_PZ_LOZ \
 109                                 | DDRCDR_NZ_LOZ \
 110                                 | DDRCDR_ODT \
 111                                 | DDRCDR_Q_DRN)
 112                                 /* 0x7b880001 */
 113 /*
 114  * Manually set up DDR parameters
 115  * consist of one chip NT5TU64M16HG from NANYA
 116  */
 117
 118 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 119
 120 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 121 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 122                                 | CSCONFIG_ODT_RD_NEVER \
 123                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 124                                 | CSCONFIG_BANK_BIT_3 \
 125                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 126                                 /* 0x80010102 */
 127 #define CONFIG_SYS_DDR_TIMING_3 0
 128 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 129                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 130                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 131                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 132                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 133                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 134                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 135                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 136                                 /* 0x00260802 */
 137 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 138                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 139                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 140                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 141                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 142                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 143                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 144                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 145                                 /* 0x26279222 */
 146 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 147                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 148                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 149                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 150                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 151                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 152                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 153                                 /* 0x021848c5 */
 154 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 155                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 156                                 /* 0x08240100 */
 157 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 158                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 159                                 | SDRAM_CFG_DBW_16)
 160                                 /* 0x43100000 */
 161
 162 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 163 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 164                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 165                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 166 #define CONFIG_SYS_DDR_MODE2            0x00000000
 167
 168 /*
 169  * Memory test
 170  */
 171 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 172 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 173
 174 /*
 175  * The reserved memory
 176  */
 177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 178
 179 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 180 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 181
 182 /*
 183  * Initial RAM Base Address Setup
 184  */
 185 #define CONFIG_SYS_INIT_RAM_LOCK        1
 186 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 187 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 188 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 189         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 190
 191 /*
 192  * Local Bus Configuration & Clock Setup
 193  */
 194 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 195 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 196 #define CONFIG_SYS_LBC_LBCR             0x00040000
 197
 198 /*
 199  * FLASH on the Local Bus
 200  */
 201 #if 1
 202 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 203 #define CONFIG_FLASH_CFI_LEGACY
 204 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 205 #endif
 206
 207 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 208 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 209
 210 /* Window base at flash base */
 211 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 212 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 213
 214 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 215                                 | BR_PS_16      /* 16 bit port */ \
 216                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 217                                 | BR_V)         /* valid */
 218 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 219                                 | OR_UPM_XAM \
 220                                 | OR_GPCM_CSNT \
 221                                 | OR_GPCM_ACS_DIV2 \
 222                                 | OR_GPCM_XACS \
 223                                 | OR_GPCM_SCY_15 \
 224                                 | OR_GPCM_TRLX_SET \
 225                                 | OR_GPCM_EHTR_SET)
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       135
 229
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 232
 233 /*
 234  * FPGA
 235  */
 236 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 237 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 238
 239 /* Window base at FPGA base */
 240 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 241 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 242
 243 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 244                                 | BR_PS_16      /* 16 bit port */ \
 245                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 246                                 | BR_V)         /* valid */
 247 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 248                                 | OR_UPM_XAM \
 249                                 | OR_GPCM_CSNT \
 250                                 | OR_GPCM_ACS_DIV2 \
 251                                 | OR_GPCM_XACS \
 252                                 | OR_GPCM_SCY_15 \
 253                                 | OR_GPCM_TRLX_SET \
 254                                 | OR_GPCM_EHTR_SET)
 255
 256 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 257 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 258
 259 #define CONFIG_SYS_FPGA_COUNT           1
 260
 261 #define CONFIG_SYS_MCLINK_MAX           3
 262
 263 #define CONFIG_SYS_FPGA_PTR \
 264         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 265
 266 /*
 267  * Serial Port
 268  */
 269 #define CONFIG_SYS_NS16550_SERIAL
 270 #define CONFIG_SYS_NS16550_REG_SIZE     1
 271 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 272
 273 #define CONFIG_SYS_BAUDRATE_TABLE  \
 274         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 275
 276 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 277 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 278
 279 /* Pass open firmware flat tree */
 280
 281 /* I2C */
 282 #define CONFIG_SYS_I2C
 283 #define CONFIG_SYS_I2C_FSL
 284 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 285 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 286 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 287
 288 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 289 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 290
 291 #define CONFIG_SYS_I2C_IHS
 292 #define CONFIG_SYS_I2C_IHS_CH0
 293 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 294 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 295 #define CONFIG_SYS_I2C_IHS_CH1
 296 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 297 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 298 #define CONFIG_SYS_I2C_IHS_CH2
 299 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 300 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 301 #define CONFIG_SYS_I2C_IHS_CH3
 302 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 303 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 304
 305 #ifdef CONFIG_HRCON_DH
 306 #define CONFIG_SYS_I2C_IHS_DUAL
 307 #define CONFIG_SYS_I2C_IHS_CH0_1
 308 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 309 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 310 #define CONFIG_SYS_I2C_IHS_CH1_1
 311 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 312 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 313 #define CONFIG_SYS_I2C_IHS_CH2_1
 314 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 315 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 316 #define CONFIG_SYS_I2C_IHS_CH3_1
 317 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 318 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 319 #endif
 320
 321 /*
 322  * Software (bit-bang) I2C driver configuration
 323  */
 324 #define CONFIG_SYS_I2C_SOFT
 325 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 326 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 327 #define I2C_SOFT_DECLARATIONS2
 328 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 329 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 330 #define I2C_SOFT_DECLARATIONS3
 331 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 332 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 333 #define I2C_SOFT_DECLARATIONS4
 334 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 335 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 336 #define I2C_SOFT_DECLARATIONS5
 337 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 338 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 339 #define I2C_SOFT_DECLARATIONS6
 340 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 341 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 342 #define I2C_SOFT_DECLARATIONS7
 343 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 344 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 345 #define I2C_SOFT_DECLARATIONS8
 346 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 347 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 348
 349 #ifdef CONFIG_HRCON_DH
 350 #define I2C_SOFT_DECLARATIONS9
 351 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 353 #define I2C_SOFT_DECLARATIONS10
 354 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 356 #define I2C_SOFT_DECLARATIONS11
 357 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 359 #define I2C_SOFT_DECLARATIONS12
 360 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 361 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 362 #endif
 363
 364 #ifdef CONFIG_HRCON_DH
 365 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 366 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 367 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 368                                                   {12, 0x4c} }
 369 #else
 370 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 371 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 372 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 373                                                   {8, 0x4c} }
 374 #endif
 375
 376 #ifndef __ASSEMBLY__
 377 void fpga_gpio_set(unsigned int bus, int pin);
 378 void fpga_gpio_clear(unsigned int bus, int pin);
 379 int fpga_gpio_get(unsigned int bus, int pin);
 380 void fpga_control_set(unsigned int bus, int pin);
 381 void fpga_control_clear(unsigned int bus, int pin);
 382 #endif
 383
 384 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 385 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 386 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 387
 388 #ifdef CONFIG_HRCON_DH
 389 #define I2C_ACTIVE \
 390         do { \
 391                 if (I2C_ADAP_HWNR > 7) \
 392                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 393                 else \
 394                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 395         } while (0)
 396 #else
 397 #define I2C_ACTIVE      { }
 398 #endif
 399 #define I2C_TRISTATE    { }
 400 #define I2C_READ \
 401         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 402 #define I2C_SDA(bit) \
 403         do { \
 404                 if (bit) \
 405                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 406                 else \
 407                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 408         } while (0)
 409 #define I2C_SCL(bit) \
 410         do { \
 411                 if (bit) \
 412                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 413                 else \
 414                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 415         } while (0)
 416 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 417
 418 /*
 419  * Software (bit-bang) MII driver configuration
 420  */
 421 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 422 #define CONFIG_BITBANGMII_MULTI
 423
 424 /*
 425  * OSD Setup
 426  */
 427 #define CONFIG_SYS_OSD_SCREENS          1
 428 #define CONFIG_SYS_DP501_DIFFERENTIAL
 429 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 430
 431 #ifdef CONFIG_HRCON_DH
 432 #define CONFIG_SYS_OSD_DH
 433 #endif
 434
 435 /*
 436  * General PCI
 437  * Addresses are mapped 1-1.
 438  */
 439 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 440 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 441 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 442 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 443 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 444 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 445 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 446 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 447 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 448
 449 /* enable PCIE clock */
 450 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 451
 452 #define CONFIG_PCI_INDIRECT_BRIDGE
 453 #define CONFIG_PCIE
 454
 455 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 456 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 457
 458 /*
 459  * TSEC
 460  */
 461 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 462 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 463
 464 /*
 465  * TSEC ethernet configuration
 466  */
 467 #define CONFIG_TSEC1
 468 #define CONFIG_TSEC1_NAME       "eTSEC0"
 469 #define TSEC1_PHY_ADDR          1
 470 #define TSEC1_PHYIDX            0
 471 #define TSEC1_FLAGS             TSEC_GIGABIT
 472
 473 /* Options are: eTSEC[0-1] */
 474 #define CONFIG_ETHPRIME         "eTSEC0"
 475
 476 /*
 477  * Environment
 478  */
 479 #if 1
 480 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 481                                  CONFIG_SYS_MONITOR_LEN)
 482 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 483 #define CONFIG_ENV_SIZE         0x2000
 484 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 485 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 486 #else
 487 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 488 #endif
 489
 490 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 491 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 492
 493 /*
 494  * Command line configuration.
 495  */
 496
 497 /*
 498  * Miscellaneous configurable options
 499  */
 500 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 501 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 502
 503 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 504
 505 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 506
 507 /*
 508  * For booting Linux, the board info and command line data
 509  * have to be in the first 256 MB of memory, since this is
 510  * the maximum mapped by the Linux kernel during initialization.
 511  */
 512 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 513
 514 /*
 515  * Core HID Setup
 516  */
 517 #define CONFIG_SYS_HID0_INIT    0x000000000
 518 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 519                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 520                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 521 #define CONFIG_SYS_HID2         HID2_HBE
 522
 523 /*
 524  * MMU Setup
 525  */
 526
 527 /* DDR: cache cacheable */
 528 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 529                                         BATL_MEMCOHERENCE)
 530 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 531                                         BATU_VS | BATU_VP)
 532 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 533 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 534
 535 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 536 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 537                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 538 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 539                                         BATU_VP)
 540 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 541 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 542
 543 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 544 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 545                                         BATL_MEMCOHERENCE)
 546 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 547                                         BATU_VS | BATU_VP)
 548 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 549                                         BATL_CACHEINHIBIT | \
 550                                         BATL_GUARDEDSTORAGE)
 551 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 552
 553 /* Stack in dcache: cacheable, no memory coherence */
 554 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 555 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 556                                         BATU_VS | BATU_VP)
 557 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 558 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 559
 560 /*
 561  * Environment Configuration
 562  */
 563
 564 #define CONFIG_ENV_OVERWRITE
 565
 566 #if defined(CONFIG_TSEC_ENET)
 567 #define CONFIG_HAS_ETH0
 568 #endif
 569
 570 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 571
 572
 573 #define CONFIG_HOSTNAME         "hrcon"
 574 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 575 #define CONFIG_BOOTFILE         "uImage"
 576
 577 #define CONFIG_PREBOOT          /* enable preboot variable */
 578
 579 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 580         "netdev=eth0\0"                                                 \
 581         "consoledev=ttyS1\0"                                            \
 582         "u-boot=u-boot.bin\0"                                           \
 583         "kernel_addr=1000000\0"                                 \
 584         "fdt_addr=C00000\0"                                             \
 585         "fdtfile=hrcon.dtb\0"                           \
 586         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 587         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 588                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 589                 " +${filesize};cp.b ${fileaddr} "                       \
 590                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 591         "upd=run load update\0"                                         \
 592
 593 #define CONFIG_NFSBOOTCOMMAND                                           \
 594         "setenv bootargs root=/dev/nfs rw "                             \
 595         "nfsroot=$serverip:$rootpath "                                  \
 596         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 597         "console=$consoledev,$baudrate $othbootargs;"                   \
 598         "tftp ${kernel_addr} $bootfile;"                                \
 599         "tftp ${fdt_addr} $fdtfile;"                                    \
 600         "bootm ${kernel_addr} - ${fdt_addr}"
 601
 602 #define CONFIG_MMCBOOTCOMMAND                                           \
 603         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 604         "console=$consoledev,$baudrate $othbootargs;"                   \
 605         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 606         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 607         "bootm ${kernel_addr} - ${fdt_addr}"
 608
 609 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 610
 611 #endif  /* __CONFIG_H */