include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  17
  18 /*
  19  * SERDES
  20  */
  21 #define CONFIG_FSL_SERDES
  22 #define CONFIG_FSL_SERDES1      0xe3000
  23
  24 /*
  25  * Arbiter Setup
  26  */
  27 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  28 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  29 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  30
  31 /*
  32  * DDR Setup
  33  */
  34 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  35 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  36 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  37 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  38 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  39                                 | DDRCDR_PZ_LOZ \
  40                                 | DDRCDR_NZ_LOZ \
  41                                 | DDRCDR_ODT \
  42                                 | DDRCDR_Q_DRN)
  43                                 /* 0x7b880001 */
  44 /*
  45  * Manually set up DDR parameters
  46  * consist of one chip NT5TU64M16HG from NANYA
  47  */
  48
  49 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  50
  51 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  52 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  53                                 | CSCONFIG_ODT_RD_NEVER \
  54                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  55                                 | CSCONFIG_BANK_BIT_3 \
  56                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  57                                 /* 0x80010102 */
  58 #define CONFIG_SYS_DDR_TIMING_3 0
  59 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  60                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  61                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  62                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  64                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  65                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  66                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  67                                 /* 0x00260802 */
  68 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  69                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  70                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  71                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  72                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  73                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  74                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  75                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  76                                 /* 0x26279222 */
  77 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  78                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  79                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  80                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  81                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  82                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  83                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  84                                 /* 0x021848c5 */
  85 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  86                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  87                                 /* 0x08240100 */
  88 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  89                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  90                                 | SDRAM_CFG_DBW_16)
  91                                 /* 0x43100000 */
  92
  93 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  94 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  95                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
  96                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
  97 #define CONFIG_SYS_DDR_MODE2            0x00000000
  98
  99 /*
 100  * Memory test
 101  */
 102 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 103 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 104
 105 /*
 106  * The reserved memory
 107  */
 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 109
 110 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 111 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 112
 113 /*
 114  * Initial RAM Base Address Setup
 115  */
 116 #define CONFIG_SYS_INIT_RAM_LOCK        1
 117 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 118 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 119 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 120         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 121
 122 /*
 123  * Local Bus Configuration & Clock Setup
 124  */
 125 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 126 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 127 #define CONFIG_SYS_LBC_LBCR             0x00040000
 128
 129 /*
 130  * FLASH on the Local Bus
 131  */
 132 #if 1
 133 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 134 #define CONFIG_FLASH_CFI_LEGACY
 135 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 136 #endif
 137
 138 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 139 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 140
 141
 142 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 143 #define CONFIG_SYS_MAX_FLASH_SECT       135
 144
 145 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 146 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 147
 148 /*
 149  * FPGA
 150  */
 151 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 152 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 153
 154
 155 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 156 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 157
 158 #define CONFIG_SYS_FPGA_COUNT           1
 159
 160 #define CONFIG_SYS_MCLINK_MAX           3
 161
 162 #define CONFIG_SYS_FPGA_PTR \
 163         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 164
 165 /*
 166  * Serial Port
 167  */
 168 #define CONFIG_SYS_NS16550_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 171
 172 #define CONFIG_SYS_BAUDRATE_TABLE  \
 173         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 174
 175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 177
 178 /* Pass open firmware flat tree */
 179
 180 /* I2C */
 181 #define CONFIG_SYS_I2C
 182 #define CONFIG_SYS_I2C_FSL
 183 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 184 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 185 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 186
 187 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 188 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 189
 190 #define CONFIG_SYS_I2C_IHS
 191 #define CONFIG_SYS_I2C_IHS_CH0
 192 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 193 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 194 #define CONFIG_SYS_I2C_IHS_CH1
 195 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 196 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 197 #define CONFIG_SYS_I2C_IHS_CH2
 198 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 199 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 200 #define CONFIG_SYS_I2C_IHS_CH3
 201 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 202 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 203
 204 #ifdef CONFIG_HRCON_DH
 205 #define CONFIG_SYS_I2C_IHS_DUAL
 206 #define CONFIG_SYS_I2C_IHS_CH0_1
 207 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 208 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 209 #define CONFIG_SYS_I2C_IHS_CH1_1
 210 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 211 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 212 #define CONFIG_SYS_I2C_IHS_CH2_1
 213 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 214 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 215 #define CONFIG_SYS_I2C_IHS_CH3_1
 216 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 217 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 218 #endif
 219
 220 /*
 221  * Software (bit-bang) I2C driver configuration
 222  */
 223 #define CONFIG_SYS_I2C_SOFT
 224 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 225 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 226 #define I2C_SOFT_DECLARATIONS2
 227 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 228 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 229 #define I2C_SOFT_DECLARATIONS3
 230 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 231 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 232 #define I2C_SOFT_DECLARATIONS4
 233 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 234 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 235 #define I2C_SOFT_DECLARATIONS5
 236 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 237 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 238 #define I2C_SOFT_DECLARATIONS6
 239 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 240 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 241 #define I2C_SOFT_DECLARATIONS7
 242 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 243 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 244 #define I2C_SOFT_DECLARATIONS8
 245 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 246 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 247
 248 #ifdef CONFIG_HRCON_DH
 249 #define I2C_SOFT_DECLARATIONS9
 250 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 251 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 252 #define I2C_SOFT_DECLARATIONS10
 253 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 254 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 255 #define I2C_SOFT_DECLARATIONS11
 256 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 257 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 258 #define I2C_SOFT_DECLARATIONS12
 259 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 260 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 261 #endif
 262
 263 #ifdef CONFIG_HRCON_DH
 264 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 265 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 266 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 267                                                   {12, 0x4c} }
 268 #else
 269 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 270 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 271 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 272                                                   {8, 0x4c} }
 273 #endif
 274
 275 #ifndef __ASSEMBLY__
 276 void fpga_gpio_set(unsigned int bus, int pin);
 277 void fpga_gpio_clear(unsigned int bus, int pin);
 278 int fpga_gpio_get(unsigned int bus, int pin);
 279 void fpga_control_set(unsigned int bus, int pin);
 280 void fpga_control_clear(unsigned int bus, int pin);
 281 #endif
 282
 283 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 284 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 285 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 286
 287 #ifdef CONFIG_HRCON_DH
 288 #define I2C_ACTIVE \
 289         do { \
 290                 if (I2C_ADAP_HWNR > 7) \
 291                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 292                 else \
 293                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 294         } while (0)
 295 #else
 296 #define I2C_ACTIVE      { }
 297 #endif
 298 #define I2C_TRISTATE    { }
 299 #define I2C_READ \
 300         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 301 #define I2C_SDA(bit) \
 302         do { \
 303                 if (bit) \
 304                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 305                 else \
 306                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 307         } while (0)
 308 #define I2C_SCL(bit) \
 309         do { \
 310                 if (bit) \
 311                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 312                 else \
 313                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 314         } while (0)
 315 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 316
 317 /*
 318  * Software (bit-bang) MII driver configuration
 319  */
 320 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 321 #define CONFIG_BITBANGMII_MULTI
 322
 323 /*
 324  * OSD Setup
 325  */
 326 #define CONFIG_SYS_OSD_SCREENS          1
 327 #define CONFIG_SYS_DP501_DIFFERENTIAL
 328 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 329
 330 #ifdef CONFIG_HRCON_DH
 331 #define CONFIG_SYS_OSD_DH
 332 #endif
 333
 334 /*
 335  * General PCI
 336  * Addresses are mapped 1-1.
 337  */
 338 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 339 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 340 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 341 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 342 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 343 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 344 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 345 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 346 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 347
 348 /* enable PCIE clock */
 349 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 350
 351 #define CONFIG_PCI_INDIRECT_BRIDGE
 352 #define CONFIG_PCIE
 353
 354 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 355 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 356
 357 /*
 358  * TSEC
 359  */
 360 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 361 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 362
 363 /*
 364  * TSEC ethernet configuration
 365  */
 366 #define CONFIG_TSEC1
 367 #define CONFIG_TSEC1_NAME       "eTSEC0"
 368 #define TSEC1_PHY_ADDR          1
 369 #define TSEC1_PHYIDX            0
 370 #define TSEC1_FLAGS             TSEC_GIGABIT
 371
 372 /* Options are: eTSEC[0-1] */
 373 #define CONFIG_ETHPRIME         "eTSEC0"
 374
 375 /*
 376  * Environment
 377  */
 378 #if 1
 379 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 380                                  CONFIG_SYS_MONITOR_LEN)
 381 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 382 #define CONFIG_ENV_SIZE         0x2000
 383 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 384 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 385 #else
 386 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 387 #endif
 388
 389 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 390 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 391
 392 /*
 393  * Command line configuration.
 394  */
 395
 396 /*
 397  * Miscellaneous configurable options
 398  */
 399 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 400 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 401
 402 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 403
 404 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 405
 406 /*
 407  * For booting Linux, the board info and command line data
 408  * have to be in the first 256 MB of memory, since this is
 409  * the maximum mapped by the Linux kernel during initialization.
 410  */
 411 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 412
 413 /*
 414  * Environment Configuration
 415  */
 416
 417 #define CONFIG_ENV_OVERWRITE
 418
 419 #if defined(CONFIG_TSEC_ENET)
 420 #define CONFIG_HAS_ETH0
 421 #endif
 422
 423 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 424
 425
 426 #define CONFIG_HOSTNAME         "hrcon"
 427 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 428 #define CONFIG_BOOTFILE         "uImage"
 429
 430 #define CONFIG_PREBOOT          /* enable preboot variable */
 431
 432 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 433         "netdev=eth0\0"                                                 \
 434         "consoledev=ttyS1\0"                                            \
 435         "u-boot=u-boot.bin\0"                                           \
 436         "kernel_addr=1000000\0"                                 \
 437         "fdt_addr=C00000\0"                                             \
 438         "fdtfile=hrcon.dtb\0"                           \
 439         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 440         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 441                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 442                 " +${filesize};cp.b ${fileaddr} "                       \
 443                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 444         "upd=run load update\0"                                         \
 445
 446 #define CONFIG_NFSBOOTCOMMAND                                           \
 447         "setenv bootargs root=/dev/nfs rw "                             \
 448         "nfsroot=$serverip:$rootpath "                                  \
 449         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 450         "console=$consoledev,$baudrate $othbootargs;"                   \
 451         "tftp ${kernel_addr} $bootfile;"                                \
 452         "tftp ${fdt_addr} $fdtfile;"                                    \
 453         "bootm ${kernel_addr} - ${fdt_addr}"
 454
 455 #define CONFIG_MMCBOOTCOMMAND                                           \
 456         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 457         "console=$consoledev,$baudrate $othbootargs;"                   \
 458         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 459         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 460         "bootm ${kernel_addr} - ${fdt_addr}"
 461
 462 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 463
 464 #endif  /* __CONFIG_H */