1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
15 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
22 #define CONFIG_SYS_SICRH (\
28 SICRH_IEEE1588_A_GPIO |\
31 SICRH_IEEE1588_B_GPIO |\
36 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
37 #define CONFIG_SYS_SICRL (\
42 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
47 #define CONFIG_SYS_IMMR 0xE0000000
52 #define CONFIG_FSL_SERDES
53 #define CONFIG_FSL_SERDES1 0xe3000
58 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
59 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
60 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
65 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
69 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
76 * Manually set up DDR parameters
77 * consist of one chip NT5TU64M16HG from NANYA
80 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
82 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
83 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
84 | CSCONFIG_ODT_RD_NEVER \
85 | CSCONFIG_ODT_WR_ONLY_CURRENT \
86 | CSCONFIG_BANK_BIT_3 \
87 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
89 #define CONFIG_SYS_DDR_TIMING_3 0
90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91 | (0 << TIMING_CFG0_WRT_SHIFT) \
92 | (0 << TIMING_CFG0_RRT_SHIFT) \
93 | (0 << TIMING_CFG0_WWT_SHIFT) \
94 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
99 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
103 | (9 << TIMING_CFG1_REFREC_SHIFT) \
104 | (2 << TIMING_CFG1_WRREC_SHIFT) \
105 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106 | (2 << TIMING_CFG1_WRTORD_SHIFT))
108 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
109 | (4 << TIMING_CFG2_CPO_SHIFT) \
110 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
116 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
117 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
119 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
120 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
124 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
125 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
126 | (0x0242 << SDRAM_MODE_SD_SHIFT))
127 /* ODT 150ohm CL=4, AL=0 on SDRAM */
128 #define CONFIG_SYS_DDR_MODE2 0x00000000
133 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
134 #define CONFIG_SYS_MEMTEST_END 0x07f00000
137 * The reserved memory
139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
141 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
142 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
145 * Initial RAM Base Address Setup
147 #define CONFIG_SYS_INIT_RAM_LOCK 1
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
150 #define CONFIG_SYS_GBL_DATA_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 * Local Bus Configuration & Clock Setup
156 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
157 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
158 #define CONFIG_SYS_LBC_LBCR 0x00040000
161 * FLASH on the Local Bus
164 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
165 #define CONFIG_FLASH_CFI_LEGACY
166 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
169 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
170 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
173 #define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
174 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
176 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
177 #define CONFIG_SYS_MAX_FLASH_SECT 135
179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
185 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
186 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
189 #define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V)
190 #define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET)
192 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
193 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
195 #define CONFIG_SYS_FPGA_COUNT 1
197 #define CONFIG_SYS_MCLINK_MAX 3
199 #define CONFIG_SYS_FPGA_PTR \
200 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
205 #define CONFIG_SYS_NS16550_SERIAL
206 #define CONFIG_SYS_NS16550_REG_SIZE 1
207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
209 #define CONFIG_SYS_BAUDRATE_TABLE \
210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
215 /* Pass open firmware flat tree */
218 #define CONFIG_SYS_I2C
219 #define CONFIG_SYS_I2C_FSL
220 #define CONFIG_SYS_FSL_I2C_SPEED 400000
221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
224 #define CONFIG_PCA953X /* NXP PCA9554 */
225 #define CONFIG_PCA9698 /* NXP PCA9698 */
227 #define CONFIG_SYS_I2C_IHS
228 #define CONFIG_SYS_I2C_IHS_CH0
229 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
230 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
231 #define CONFIG_SYS_I2C_IHS_CH1
232 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
233 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
234 #define CONFIG_SYS_I2C_IHS_CH2
235 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
236 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
237 #define CONFIG_SYS_I2C_IHS_CH3
238 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
239 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
241 #ifdef CONFIG_HRCON_DH
242 #define CONFIG_SYS_I2C_IHS_DUAL
243 #define CONFIG_SYS_I2C_IHS_CH0_1
244 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
245 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
246 #define CONFIG_SYS_I2C_IHS_CH1_1
247 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
248 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
249 #define CONFIG_SYS_I2C_IHS_CH2_1
250 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
251 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
252 #define CONFIG_SYS_I2C_IHS_CH3_1
253 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
254 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
258 * Software (bit-bang) I2C driver configuration
260 #define CONFIG_SYS_I2C_SOFT
261 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
262 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
263 #define I2C_SOFT_DECLARATIONS2
264 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
265 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
266 #define I2C_SOFT_DECLARATIONS3
267 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
268 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
269 #define I2C_SOFT_DECLARATIONS4
270 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
271 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
272 #define I2C_SOFT_DECLARATIONS5
273 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
274 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
275 #define I2C_SOFT_DECLARATIONS6
276 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
277 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
278 #define I2C_SOFT_DECLARATIONS7
279 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
280 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
281 #define I2C_SOFT_DECLARATIONS8
282 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
283 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
285 #ifdef CONFIG_HRCON_DH
286 #define I2C_SOFT_DECLARATIONS9
287 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
288 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
289 #define I2C_SOFT_DECLARATIONS10
290 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
291 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
292 #define I2C_SOFT_DECLARATIONS11
293 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
294 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
295 #define I2C_SOFT_DECLARATIONS12
296 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
297 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
300 #ifdef CONFIG_HRCON_DH
301 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
302 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
303 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
306 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
307 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
308 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
313 void fpga_gpio_set(unsigned int bus, int pin);
314 void fpga_gpio_clear(unsigned int bus, int pin);
315 int fpga_gpio_get(unsigned int bus, int pin);
316 void fpga_control_set(unsigned int bus, int pin);
317 void fpga_control_clear(unsigned int bus, int pin);
320 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
321 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
322 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
324 #ifdef CONFIG_HRCON_DH
327 if (I2C_ADAP_HWNR > 7) \
328 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
330 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
333 #define I2C_ACTIVE { }
335 #define I2C_TRISTATE { }
337 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
338 #define I2C_SDA(bit) \
341 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
343 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
345 #define I2C_SCL(bit) \
348 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
350 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
352 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
355 * Software (bit-bang) MII driver configuration
357 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
358 #define CONFIG_BITBANGMII_MULTI
363 #define CONFIG_SYS_OSD_SCREENS 1
364 #define CONFIG_SYS_DP501_DIFFERENTIAL
365 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
367 #ifdef CONFIG_HRCON_DH
368 #define CONFIG_SYS_OSD_DH
373 * Addresses are mapped 1-1.
375 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
376 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
377 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
378 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
379 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
380 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
381 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
383 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
385 /* enable PCIE clock */
386 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
388 #define CONFIG_PCI_INDIRECT_BRIDGE
391 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
392 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
397 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
398 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
401 * TSEC ethernet configuration
404 #define CONFIG_TSEC1_NAME "eTSEC0"
405 #define TSEC1_PHY_ADDR 1
406 #define TSEC1_PHYIDX 0
407 #define TSEC1_FLAGS TSEC_GIGABIT
409 /* Options are: eTSEC[0-1] */
410 #define CONFIG_ETHPRIME "eTSEC0"
416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
417 CONFIG_SYS_MONITOR_LEN)
418 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
419 #define CONFIG_ENV_SIZE 0x2000
420 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
421 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
423 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
426 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
427 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
430 * Command line configuration.
434 * Miscellaneous configurable options
436 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
437 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
439 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
441 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
444 * For booting Linux, the board info and command line data
445 * have to be in the first 256 MB of memory, since this is
446 * the maximum mapped by the Linux kernel during initialization.
448 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
453 #define CONFIG_SYS_HID0_INIT 0x000000000
454 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
455 HID0_ENABLE_INSTRUCTION_CACHE | \
456 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
457 #define CONFIG_SYS_HID2 HID2_HBE
460 * Environment Configuration
463 #define CONFIG_ENV_OVERWRITE
465 #if defined(CONFIG_TSEC_ENET)
466 #define CONFIG_HAS_ETH0
469 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
472 #define CONFIG_HOSTNAME "hrcon"
473 #define CONFIG_ROOTPATH "/opt/nfsroot"
474 #define CONFIG_BOOTFILE "uImage"
476 #define CONFIG_PREBOOT /* enable preboot variable */
478 #define CONFIG_EXTRA_ENV_SETTINGS \
480 "consoledev=ttyS1\0" \
481 "u-boot=u-boot.bin\0" \
482 "kernel_addr=1000000\0" \
483 "fdt_addr=C00000\0" \
484 "fdtfile=hrcon.dtb\0" \
485 "load=tftp ${loadaddr} ${u-boot}\0" \
486 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
487 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
488 " +${filesize};cp.b ${fileaddr} " \
489 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
490 "upd=run load update\0" \
492 #define CONFIG_NFSBOOTCOMMAND \
493 "setenv bootargs root=/dev/nfs rw " \
494 "nfsroot=$serverip:$rootpath " \
495 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
496 "console=$consoledev,$baudrate $othbootargs;" \
497 "tftp ${kernel_addr} $bootfile;" \
498 "tftp ${fdt_addr} $fdtfile;" \
499 "bootm ${kernel_addr} - ${fdt_addr}"
501 #define CONFIG_MMCBOOTCOMMAND \
502 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
503 "console=$consoledev,$baudrate $othbootargs;" \
504 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
505 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
506 "bootm ${kernel_addr} - ${fdt_addr}"
508 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
510 #endif /* __CONFIG_H */