3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
6 * SPDX-License-Identifier: GPL-2.0+
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_MPC830x 1 /* MPC830x family */
18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
19 #define CONFIG_HRCON 1 /* HRCON board specific */
21 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
26 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
27 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
30 * Hardware Reset Configuration Word
31 * if CLKIN is 66.66MHz, then
32 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
33 * We choose the A type silicon as default, so the core is 400Mhz.
35 #define CONFIG_SYS_HRCW_LOW (\
36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
37 HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 HRCWL_CSB_TO_CLKIN_4X1 |\
40 HRCWL_CORE_TO_CSB_3X1)
42 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
43 * in 8308's HRCWH according to the manual, but original Freescale's
44 * code has them and I've expirienced some problems using the board
45 * with BDI3000 attached when I've tried to set these bits to zero
46 * (UART doesn't work after the 'reset run' command).
48 #define CONFIG_SYS_HRCW_HIGH (\
50 HRCWH_PCI1_ARBITER_ENABLE |\
52 HRCWH_FROM_0XFFF00100 |\
53 HRCWH_BOOTSEQ_DISABLE |\
54 HRCWH_SW_WATCHDOG_DISABLE |\
55 HRCWH_ROM_LOC_LOCAL_16BIT |\
56 HRCWH_RL_EXT_LEGACY |\
57 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
64 #define CONFIG_SYS_SICRH (\
70 SICRH_IEEE1588_A_GPIO |\
73 SICRH_IEEE1588_B_GPIO |\
78 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
79 #define CONFIG_SYS_SICRL (\
84 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
89 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_FSL_SERDES
95 #define CONFIG_FSL_SERDES1 0xe3000
100 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
101 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
102 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
107 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
109 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
111 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
118 * Manually set up DDR parameters
119 * consist of one chip NT5TU64M16HG from NANYA
122 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
124 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
125 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
126 | CSCONFIG_ODT_RD_NEVER \
127 | CSCONFIG_ODT_WR_ONLY_CURRENT \
128 | CSCONFIG_BANK_BIT_3 \
129 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
131 #define CONFIG_SYS_DDR_TIMING_3 0
132 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
133 | (0 << TIMING_CFG0_WRT_SHIFT) \
134 | (0 << TIMING_CFG0_RRT_SHIFT) \
135 | (0 << TIMING_CFG0_WWT_SHIFT) \
136 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
137 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
138 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
139 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
141 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
142 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
143 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
144 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
145 | (9 << TIMING_CFG1_REFREC_SHIFT) \
146 | (2 << TIMING_CFG1_WRREC_SHIFT) \
147 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
148 | (2 << TIMING_CFG1_WRTORD_SHIFT))
150 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
151 | (4 << TIMING_CFG2_CPO_SHIFT) \
152 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
153 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
154 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
155 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
156 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
158 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
159 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
161 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
162 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
166 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
167 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
168 | (0x0242 << SDRAM_MODE_SD_SHIFT))
169 /* ODT 150ohm CL=4, AL=0 on SDRAM */
170 #define CONFIG_SYS_DDR_MODE2 0x00000000
175 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
176 #define CONFIG_SYS_MEMTEST_END 0x07f00000
179 * The reserved memory
181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
183 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
184 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
187 * Initial RAM Base Address Setup
189 #define CONFIG_SYS_INIT_RAM_LOCK 1
190 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
191 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
192 #define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196 * Local Bus Configuration & Clock Setup
198 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
199 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
200 #define CONFIG_SYS_LBC_LBCR 0x00040000
203 * FLASH on the Local Bus
206 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
207 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
208 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
209 #define CONFIG_FLASH_CFI_LEGACY
210 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
213 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
214 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
215 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
217 /* Window base at flash base */
218 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
219 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
221 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
222 | BR_PS_16 /* 16 bit port */ \
223 | BR_MS_GPCM /* MSEL = GPCM */ \
225 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
234 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
235 #define CONFIG_SYS_MAX_FLASH_SECT 135
237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
243 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
244 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
246 /* Window base at FPGA base */
247 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
248 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
250 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
251 | BR_PS_16 /* 16 bit port */ \
252 | BR_MS_GPCM /* MSEL = GPCM */ \
254 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
263 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
264 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
266 #define CONFIG_SYS_FPGA_COUNT 1
268 #define CONFIG_SYS_MCLINK_MAX 3
270 #define CONFIG_SYS_FPGA_PTR \
271 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
276 #define CONFIG_SYS_NS16550_SERIAL
277 #define CONFIG_SYS_NS16550_REG_SIZE 1
278 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
280 #define CONFIG_SYS_BAUDRATE_TABLE \
281 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
283 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
284 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
286 /* Pass open firmware flat tree */
289 #define CONFIG_SYS_I2C
290 #define CONFIG_SYS_I2C_FSL
291 #define CONFIG_SYS_FSL_I2C_SPEED 400000
292 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
293 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
295 #define CONFIG_PCA953X /* NXP PCA9554 */
296 #define CONFIG_PCA9698 /* NXP PCA9698 */
298 #define CONFIG_SYS_I2C_IHS
299 #define CONFIG_SYS_I2C_IHS_CH0
300 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
301 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
302 #define CONFIG_SYS_I2C_IHS_CH1
303 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
304 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
305 #define CONFIG_SYS_I2C_IHS_CH2
306 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
307 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
308 #define CONFIG_SYS_I2C_IHS_CH3
309 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
310 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
312 #ifdef CONFIG_HRCON_DH
313 #define CONFIG_SYS_I2C_IHS_DUAL
314 #define CONFIG_SYS_I2C_IHS_CH0_1
315 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
316 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
317 #define CONFIG_SYS_I2C_IHS_CH1_1
318 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
319 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
320 #define CONFIG_SYS_I2C_IHS_CH2_1
321 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
322 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
323 #define CONFIG_SYS_I2C_IHS_CH3_1
324 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
325 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
329 * Software (bit-bang) I2C driver configuration
331 #define CONFIG_SYS_I2C_SOFT
332 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
333 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
334 #define I2C_SOFT_DECLARATIONS2
335 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
336 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
337 #define I2C_SOFT_DECLARATIONS3
338 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
339 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
340 #define I2C_SOFT_DECLARATIONS4
341 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
342 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
343 #define I2C_SOFT_DECLARATIONS5
344 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
345 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
346 #define I2C_SOFT_DECLARATIONS6
347 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
348 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
349 #define I2C_SOFT_DECLARATIONS7
350 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
351 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
352 #define I2C_SOFT_DECLARATIONS8
353 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
354 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
356 #ifdef CONFIG_HRCON_DH
357 #define I2C_SOFT_DECLARATIONS9
358 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
359 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
360 #define I2C_SOFT_DECLARATIONS10
361 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
362 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
363 #define I2C_SOFT_DECLARATIONS11
364 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
366 #define I2C_SOFT_DECLARATIONS12
367 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
371 #ifdef CONFIG_HRCON_DH
372 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
373 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
374 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
377 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
378 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
379 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
384 void fpga_gpio_set(unsigned int bus, int pin);
385 void fpga_gpio_clear(unsigned int bus, int pin);
386 int fpga_gpio_get(unsigned int bus, int pin);
387 void fpga_control_set(unsigned int bus, int pin);
388 void fpga_control_clear(unsigned int bus, int pin);
391 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
392 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
393 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
395 #ifdef CONFIG_HRCON_DH
398 if (I2C_ADAP_HWNR > 7) \
399 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
401 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
404 #define I2C_ACTIVE { }
406 #define I2C_TRISTATE { }
408 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
409 #define I2C_SDA(bit) \
412 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
414 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
416 #define I2C_SCL(bit) \
419 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
421 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
423 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
426 * Software (bit-bang) MII driver configuration
428 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
429 #define CONFIG_BITBANGMII_MULTI
434 #define CONFIG_SYS_OSD_SCREENS 1
435 #define CONFIG_SYS_DP501_DIFFERENTIAL
436 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
438 #ifdef CONFIG_HRCON_DH
439 #define CONFIG_SYS_OSD_DH
444 * Addresses are mapped 1-1.
446 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
447 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
449 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
450 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
451 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
452 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
453 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
454 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
456 /* enable PCIE clock */
457 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
459 #define CONFIG_PCI_INDIRECT_BRIDGE
462 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
463 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
468 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
469 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
472 * TSEC ethernet configuration
474 #define CONFIG_MII 1 /* MII PHY management */
476 #define CONFIG_TSEC1_NAME "eTSEC0"
477 #define TSEC1_PHY_ADDR 1
478 #define TSEC1_PHYIDX 0
479 #define TSEC1_FLAGS TSEC_GIGABIT
481 /* Options are: eTSEC[0-1] */
482 #define CONFIG_ETHPRIME "eTSEC0"
488 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
489 CONFIG_SYS_MONITOR_LEN)
490 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
491 #define CONFIG_ENV_SIZE 0x2000
492 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
493 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
495 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
498 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
499 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
502 * Command line configuration.
506 * Miscellaneous configurable options
508 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
509 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
511 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
513 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
516 * For booting Linux, the board info and command line data
517 * have to be in the first 256 MB of memory, since this is
518 * the maximum mapped by the Linux kernel during initialization.
520 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
525 #define CONFIG_SYS_HID0_INIT 0x000000000
526 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
527 HID0_ENABLE_INSTRUCTION_CACHE | \
528 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
529 #define CONFIG_SYS_HID2 HID2_HBE
535 /* DDR: cache cacheable */
536 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
538 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
540 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
541 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
543 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
544 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
545 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
546 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
548 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
549 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
551 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
552 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
554 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
556 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
557 BATL_CACHEINHIBIT | \
559 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
561 /* Stack in dcache: cacheable, no memory coherence */
562 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
563 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
565 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
566 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
569 * Environment Configuration
572 #define CONFIG_ENV_OVERWRITE
574 #if defined(CONFIG_TSEC_ENET)
575 #define CONFIG_HAS_ETH0
578 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
581 #define CONFIG_HOSTNAME hrcon
582 #define CONFIG_ROOTPATH "/opt/nfsroot"
583 #define CONFIG_BOOTFILE "uImage"
585 #define CONFIG_PREBOOT /* enable preboot variable */
587 #define CONFIG_EXTRA_ENV_SETTINGS \
589 "consoledev=ttyS1\0" \
590 "u-boot=u-boot.bin\0" \
591 "kernel_addr=1000000\0" \
592 "fdt_addr=C00000\0" \
593 "fdtfile=hrcon.dtb\0" \
594 "load=tftp ${loadaddr} ${u-boot}\0" \
595 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
596 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
597 " +${filesize};cp.b ${fileaddr} " \
598 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
599 "upd=run load update\0" \
601 #define CONFIG_NFSBOOTCOMMAND \
602 "setenv bootargs root=/dev/nfs rw " \
603 "nfsroot=$serverip:$rootpath " \
604 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
605 "console=$consoledev,$baudrate $othbootargs;" \
606 "tftp ${kernel_addr} $bootfile;" \
607 "tftp ${fdt_addr} $fdtfile;" \
608 "bootm ${kernel_addr} - ${fdt_addr}"
610 #define CONFIG_MMCBOOTCOMMAND \
611 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
612 "console=$consoledev,$baudrate $othbootargs;" \
613 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
614 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
615 "bootm ${kernel_addr} - ${fdt_addr}"
617 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
619 #endif /* __CONFIG_H */