include/configs/hrcon.h

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  17 #define CONFIG_MPC830x          1 /* MPC830x family */
  18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  19 #define CONFIG_HRCON            1 /* HRCON board specific */
  20
  21 #define CONFIG_LAST_STAGE_INIT
  22
  23 #define CONFIG_FSL_ESDHC
  24 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  25
  26 /*
  27  * System Clock Setup
  28  */
  29 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  30 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  31
  32 /*
  33  * Hardware Reset Configuration Word
  34  * if CLKIN is 66.66MHz, then
  35  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  36  * We choose the A type silicon as default, so the core is 400Mhz.
  37  */
  38 #define CONFIG_SYS_HRCW_LOW (\
  39         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  40         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  41         HRCWL_SVCOD_DIV_2 |\
  42         HRCWL_CSB_TO_CLKIN_4X1 |\
  43         HRCWL_CORE_TO_CSB_3X1)
  44 /*
  45  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  46  * in 8308's HRCWH according to the manual, but original Freescale's
  47  * code has them and I've expirienced some problems using the board
  48  * with BDI3000 attached when I've tried to set these bits to zero
  49  * (UART doesn't work after the 'reset run' command).
  50  */
  51 #define CONFIG_SYS_HRCW_HIGH (\
  52         HRCWH_PCI_HOST |\
  53         HRCWH_PCI1_ARBITER_ENABLE |\
  54         HRCWH_CORE_ENABLE |\
  55         HRCWH_FROM_0XFFF00100 |\
  56         HRCWH_BOOTSEQ_DISABLE |\
  57         HRCWH_SW_WATCHDOG_DISABLE |\
  58         HRCWH_ROM_LOC_LOCAL_16BIT |\
  59         HRCWH_RL_EXT_LEGACY |\
  60         HRCWH_TSEC1M_IN_RGMII |\
  61         HRCWH_TSEC2M_IN_RGMII |\
  62         HRCWH_BIG_ENDIAN)
  63
  64 /*
  65  * System IO Config
  66  */
  67 #define CONFIG_SYS_SICRH (\
  68         SICRH_ESDHC_A_SD |\
  69         SICRH_ESDHC_B_SD |\
  70         SICRH_ESDHC_C_SD |\
  71         SICRH_GPIO_A_GPIO |\
  72         SICRH_GPIO_B_GPIO |\
  73         SICRH_IEEE1588_A_GPIO |\
  74         SICRH_USB |\
  75         SICRH_GTM_GPIO |\
  76         SICRH_IEEE1588_B_GPIO |\
  77         SICRH_ETSEC2_GPIO |\
  78         SICRH_GPIOSEL_1 |\
  79         SICRH_TMROBI_V3P3 |\
  80         SICRH_TSOBI1_V2P5 |\
  81         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  82 #define CONFIG_SYS_SICRL (\
  83         SICRL_SPI_PF0 |\
  84         SICRL_UART_PF0 |\
  85         SICRL_IRQ_PF0 |\
  86         SICRL_I2C2_PF0 |\
  87         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  88
  89 /*
  90  * IMMR new address
  91  */
  92 #define CONFIG_SYS_IMMR         0xE0000000
  93
  94 /*
  95  * SERDES
  96  */
  97 #define CONFIG_FSL_SERDES
  98 #define CONFIG_FSL_SERDES1      0xe3000
  99
 100 /*
 101  * Arbiter Setup
 102  */
 103 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 104 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 105 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 106
 107 /*
 108  * DDR Setup
 109  */
 110 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 111 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 112 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 113 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 114 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 115                                 | DDRCDR_PZ_LOZ \
 116                                 | DDRCDR_NZ_LOZ \
 117                                 | DDRCDR_ODT \
 118                                 | DDRCDR_Q_DRN)
 119                                 /* 0x7b880001 */
 120 /*
 121  * Manually set up DDR parameters
 122  * consist of one chip NT5TU64M16HG from NANYA
 123  */
 124
 125 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 126
 127 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 128 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 129                                 | CSCONFIG_ODT_RD_NEVER \
 130                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 131                                 | CSCONFIG_BANK_BIT_3 \
 132                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 133                                 /* 0x80010102 */
 134 #define CONFIG_SYS_DDR_TIMING_3 0
 135 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 136                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 137                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 138                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 139                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 140                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 141                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 142                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 143                                 /* 0x00260802 */
 144 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 145                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 146                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 147                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 148                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 149                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 150                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 151                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 152                                 /* 0x26279222 */
 153 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 154                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 155                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 156                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 157                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 158                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 159                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 160                                 /* 0x021848c5 */
 161 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 162                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 163                                 /* 0x08240100 */
 164 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 165                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 166                                 | SDRAM_CFG_DBW_16)
 167                                 /* 0x43100000 */
 168
 169 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 170 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 171                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 172                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 173 #define CONFIG_SYS_DDR_MODE2            0x00000000
 174
 175 /*
 176  * Memory test
 177  */
 178 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 179 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 180
 181 /*
 182  * The reserved memory
 183  */
 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 185
 186 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 187 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 188
 189 /*
 190  * Initial RAM Base Address Setup
 191  */
 192 #define CONFIG_SYS_INIT_RAM_LOCK        1
 193 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 194 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 195 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 196         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 197
 198 /*
 199  * Local Bus Configuration & Clock Setup
 200  */
 201 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 202 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 203 #define CONFIG_SYS_LBC_LBCR             0x00040000
 204
 205 /*
 206  * FLASH on the Local Bus
 207  */
 208 #if 1
 209 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 210 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 211 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 212 #define CONFIG_FLASH_CFI_LEGACY
 213 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 214 #endif
 215
 216 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 217 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 218 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 219
 220 /* Window base at flash base */
 221 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 222 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 223
 224 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 225                                 | BR_PS_16      /* 16 bit port */ \
 226                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 227                                 | BR_V)         /* valid */
 228 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 229                                 | OR_UPM_XAM \
 230                                 | OR_GPCM_CSNT \
 231                                 | OR_GPCM_ACS_DIV2 \
 232                                 | OR_GPCM_XACS \
 233                                 | OR_GPCM_SCY_15 \
 234                                 | OR_GPCM_TRLX_SET \
 235                                 | OR_GPCM_EHTR_SET)
 236
 237 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 238 #define CONFIG_SYS_MAX_FLASH_SECT       135
 239
 240 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 241 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 242
 243 /*
 244  * FPGA
 245  */
 246 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 247 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 248
 249 /* Window base at FPGA base */
 250 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 251 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 252
 253 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 254                                 | BR_PS_16      /* 16 bit port */ \
 255                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 256                                 | BR_V)         /* valid */
 257 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 258                                 | OR_UPM_XAM \
 259                                 | OR_GPCM_CSNT \
 260                                 | OR_GPCM_ACS_DIV2 \
 261                                 | OR_GPCM_XACS \
 262                                 | OR_GPCM_SCY_15 \
 263                                 | OR_GPCM_TRLX_SET \
 264                                 | OR_GPCM_EHTR_SET)
 265
 266 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 267 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 268
 269 #define CONFIG_SYS_FPGA_COUNT           1
 270
 271 #define CONFIG_SYS_MCLINK_MAX           3
 272
 273 #define CONFIG_SYS_FPGA_PTR \
 274         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 275
 276 /*
 277  * Serial Port
 278  */
 279 #define CONFIG_SYS_NS16550_SERIAL
 280 #define CONFIG_SYS_NS16550_REG_SIZE     1
 281 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 282
 283 #define CONFIG_SYS_BAUDRATE_TABLE  \
 284         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 285
 286 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 287 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 288
 289 /* Pass open firmware flat tree */
 290
 291 /* I2C */
 292 #define CONFIG_SYS_I2C
 293 #define CONFIG_SYS_I2C_FSL
 294 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 295 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 296 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 297
 298 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 299 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 300
 301 #define CONFIG_SYS_I2C_IHS
 302 #define CONFIG_SYS_I2C_IHS_CH0
 303 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 304 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 305 #define CONFIG_SYS_I2C_IHS_CH1
 306 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 307 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 308 #define CONFIG_SYS_I2C_IHS_CH2
 309 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 310 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 311 #define CONFIG_SYS_I2C_IHS_CH3
 312 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 313 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 314
 315 #ifdef CONFIG_HRCON_DH
 316 #define CONFIG_SYS_I2C_IHS_DUAL
 317 #define CONFIG_SYS_I2C_IHS_CH0_1
 318 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 319 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 320 #define CONFIG_SYS_I2C_IHS_CH1_1
 321 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 322 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 323 #define CONFIG_SYS_I2C_IHS_CH2_1
 324 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 325 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 326 #define CONFIG_SYS_I2C_IHS_CH3_1
 327 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 328 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 329 #endif
 330
 331 /*
 332  * Software (bit-bang) I2C driver configuration
 333  */
 334 #define CONFIG_SYS_I2C_SOFT
 335 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 336 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 337 #define I2C_SOFT_DECLARATIONS2
 338 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 339 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 340 #define I2C_SOFT_DECLARATIONS3
 341 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 342 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 343 #define I2C_SOFT_DECLARATIONS4
 344 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 345 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 346 #define I2C_SOFT_DECLARATIONS5
 347 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 348 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 349 #define I2C_SOFT_DECLARATIONS6
 350 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 351 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 352 #define I2C_SOFT_DECLARATIONS7
 353 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 354 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 355 #define I2C_SOFT_DECLARATIONS8
 356 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 357 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 358
 359 #ifdef CONFIG_HRCON_DH
 360 #define I2C_SOFT_DECLARATIONS9
 361 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 362 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 363 #define I2C_SOFT_DECLARATIONS10
 364 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 365 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 366 #define I2C_SOFT_DECLARATIONS11
 367 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 368 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 369 #define I2C_SOFT_DECLARATIONS12
 370 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 371 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 372 #endif
 373
 374 #ifdef CONFIG_HRCON_DH
 375 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 376 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 377 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 378                                                   {12, 0x4c} }
 379 #else
 380 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 381 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 382 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 383                                                   {8, 0x4c} }
 384 #endif
 385
 386 #ifndef __ASSEMBLY__
 387 void fpga_gpio_set(unsigned int bus, int pin);
 388 void fpga_gpio_clear(unsigned int bus, int pin);
 389 int fpga_gpio_get(unsigned int bus, int pin);
 390 void fpga_control_set(unsigned int bus, int pin);
 391 void fpga_control_clear(unsigned int bus, int pin);
 392 #endif
 393
 394 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 395 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 396 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 397
 398 #ifdef CONFIG_HRCON_DH
 399 #define I2C_ACTIVE \
 400         do { \
 401                 if (I2C_ADAP_HWNR > 7) \
 402                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 403                 else \
 404                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 405         } while (0)
 406 #else
 407 #define I2C_ACTIVE      { }
 408 #endif
 409 #define I2C_TRISTATE    { }
 410 #define I2C_READ \
 411         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 412 #define I2C_SDA(bit) \
 413         do { \
 414                 if (bit) \
 415                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 416                 else \
 417                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 418         } while (0)
 419 #define I2C_SCL(bit) \
 420         do { \
 421                 if (bit) \
 422                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 423                 else \
 424                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 425         } while (0)
 426 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 427
 428 /*
 429  * Software (bit-bang) MII driver configuration
 430  */
 431 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 432 #define CONFIG_BITBANGMII_MULTI
 433
 434 /*
 435  * OSD Setup
 436  */
 437 #define CONFIG_SYS_OSD_SCREENS          1
 438 #define CONFIG_SYS_DP501_DIFFERENTIAL
 439 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 440
 441 #ifdef CONFIG_HRCON_DH
 442 #define CONFIG_SYS_OSD_DH
 443 #endif
 444
 445 /*
 446  * General PCI
 447  * Addresses are mapped 1-1.
 448  */
 449 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 450 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 451 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 452 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 453 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 454 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 455 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 456 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 457 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 458
 459 /* enable PCIE clock */
 460 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 461
 462 #define CONFIG_PCI_INDIRECT_BRIDGE
 463 #define CONFIG_PCIE
 464
 465 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 466 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 467
 468 /*
 469  * TSEC
 470  */
 471 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 472 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 473 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 474
 475 /*
 476  * TSEC ethernet configuration
 477  */
 478 #define CONFIG_MII              1 /* MII PHY management */
 479 #define CONFIG_TSEC1
 480 #define CONFIG_TSEC1_NAME       "eTSEC0"
 481 #define TSEC1_PHY_ADDR          1
 482 #define TSEC1_PHYIDX            0
 483 #define TSEC1_FLAGS             TSEC_GIGABIT
 484
 485 /* Options are: eTSEC[0-1] */
 486 #define CONFIG_ETHPRIME         "eTSEC0"
 487
 488 /*
 489  * Environment
 490  */
 491 #if 1
 492 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 493                                  CONFIG_SYS_MONITOR_LEN)
 494 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 495 #define CONFIG_ENV_SIZE         0x2000
 496 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 497 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 498 #else
 499 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 500 #endif
 501
 502 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 503 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 504
 505 /*
 506  * Command line configuration.
 507  */
 508
 509 /*
 510  * Miscellaneous configurable options
 511  */
 512 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 513 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 514
 515 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 516
 517 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 518
 519 /*
 520  * For booting Linux, the board info and command line data
 521  * have to be in the first 256 MB of memory, since this is
 522  * the maximum mapped by the Linux kernel during initialization.
 523  */
 524 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 525
 526 /*
 527  * Core HID Setup
 528  */
 529 #define CONFIG_SYS_HID0_INIT    0x000000000
 530 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 531                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 532                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 533 #define CONFIG_SYS_HID2         HID2_HBE
 534
 535 /*
 536  * MMU Setup
 537  */
 538
 539 /* DDR: cache cacheable */
 540 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 541                                         BATL_MEMCOHERENCE)
 542 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 543                                         BATU_VS | BATU_VP)
 544 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 545 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 546
 547 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 548 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 549                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 550 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 551                                         BATU_VP)
 552 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 553 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 554
 555 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 556 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 557                                         BATL_MEMCOHERENCE)
 558 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 559                                         BATU_VS | BATU_VP)
 560 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 561                                         BATL_CACHEINHIBIT | \
 562                                         BATL_GUARDEDSTORAGE)
 563 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 564
 565 /* Stack in dcache: cacheable, no memory coherence */
 566 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 567 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 568                                         BATU_VS | BATU_VP)
 569 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 570 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 571
 572 /*
 573  * Environment Configuration
 574  */
 575
 576 #define CONFIG_ENV_OVERWRITE
 577
 578 #if defined(CONFIG_TSEC_ENET)
 579 #define CONFIG_HAS_ETH0
 580 #endif
 581
 582 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 583
 584
 585 #define CONFIG_HOSTNAME         hrcon
 586 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 587 #define CONFIG_BOOTFILE         "uImage"
 588
 589 #define CONFIG_PREBOOT          /* enable preboot variable */
 590
 591 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 592         "netdev=eth0\0"                                                 \
 593         "consoledev=ttyS1\0"                                            \
 594         "u-boot=u-boot.bin\0"                                           \
 595         "kernel_addr=1000000\0"                                 \
 596         "fdt_addr=C00000\0"                                             \
 597         "fdtfile=hrcon.dtb\0"                           \
 598         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 599         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 600                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 601                 " +${filesize};cp.b ${fileaddr} "                       \
 602                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 603         "upd=run load update\0"                                         \
 604
 605 #define CONFIG_NFSBOOTCOMMAND                                           \
 606         "setenv bootargs root=/dev/nfs rw "                             \
 607         "nfsroot=$serverip:$rootpath "                                  \
 608         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 609         "console=$consoledev,$baudrate $othbootargs;"                   \
 610         "tftp ${kernel_addr} $bootfile;"                                \
 611         "tftp ${fdt_addr} $fdtfile;"                                    \
 612         "bootm ${kernel_addr} - ${fdt_addr}"
 613
 614 #define CONFIG_MMCBOOTCOMMAND                                           \
 615         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 616         "console=$consoledev,$baudrate $othbootargs;"                   \
 617         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 618         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 619         "bootm ${kernel_addr} - ${fdt_addr}"
 620
 621 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 622
 623 #endif  /* __CONFIG_H */