include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  16
  17 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  18
  19 /*
  20  * System IO Config
  21  */
  22 #define CONFIG_SYS_SICRH (\
  23         SICRH_ESDHC_A_SD |\
  24         SICRH_ESDHC_B_SD |\
  25         SICRH_ESDHC_C_SD |\
  26         SICRH_GPIO_A_GPIO |\
  27         SICRH_GPIO_B_GPIO |\
  28         SICRH_IEEE1588_A_GPIO |\
  29         SICRH_USB |\
  30         SICRH_GTM_GPIO |\
  31         SICRH_IEEE1588_B_GPIO |\
  32         SICRH_ETSEC2_GPIO |\
  33         SICRH_GPIOSEL_1 |\
  34         SICRH_TMROBI_V3P3 |\
  35         SICRH_TSOBI1_V2P5 |\
  36         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  37 #define CONFIG_SYS_SICRL (\
  38         SICRL_SPI_PF0 |\
  39         SICRL_UART_PF0 |\
  40         SICRL_IRQ_PF0 |\
  41         SICRL_I2C2_PF0 |\
  42         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  43
  44 /*
  45  * IMMR new address
  46  */
  47 #define CONFIG_SYS_IMMR         0xE0000000
  48
  49 /*
  50  * SERDES
  51  */
  52 #define CONFIG_FSL_SERDES
  53 #define CONFIG_FSL_SERDES1      0xe3000
  54
  55 /*
  56  * Arbiter Setup
  57  */
  58 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  59 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  60 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  61
  62 /*
  63  * DDR Setup
  64  */
  65 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  66 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  67 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  69 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  70                                 | DDRCDR_PZ_LOZ \
  71                                 | DDRCDR_NZ_LOZ \
  72                                 | DDRCDR_ODT \
  73                                 | DDRCDR_Q_DRN)
  74                                 /* 0x7b880001 */
  75 /*
  76  * Manually set up DDR parameters
  77  * consist of one chip NT5TU64M16HG from NANYA
  78  */
  79
  80 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  81
  82 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  83 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  84                                 | CSCONFIG_ODT_RD_NEVER \
  85                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  86                                 | CSCONFIG_BANK_BIT_3 \
  87                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  88                                 /* 0x80010102 */
  89 #define CONFIG_SYS_DDR_TIMING_3 0
  90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  91                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  92                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  93                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  94                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  95                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  96                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  97                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  98                                 /* 0x00260802 */
  99 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 100                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 101                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 102                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 103                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 104                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 105                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 106                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 107                                 /* 0x26279222 */
 108 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 109                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 110                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 111                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 112                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 113                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 114                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 115                                 /* 0x021848c5 */
 116 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 117                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 118                                 /* 0x08240100 */
 119 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 120                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 121                                 | SDRAM_CFG_DBW_16)
 122                                 /* 0x43100000 */
 123
 124 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 125 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 126                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 127                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 128 #define CONFIG_SYS_DDR_MODE2            0x00000000
 129
 130 /*
 131  * Memory test
 132  */
 133 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 134 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 135
 136 /*
 137  * The reserved memory
 138  */
 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 140
 141 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 142 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 143
 144 /*
 145  * Initial RAM Base Address Setup
 146  */
 147 #define CONFIG_SYS_INIT_RAM_LOCK        1
 148 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 149 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 150 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 151         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 152
 153 /*
 154  * Local Bus Configuration & Clock Setup
 155  */
 156 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 157 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 158 #define CONFIG_SYS_LBC_LBCR             0x00040000
 159
 160 /*
 161  * FLASH on the Local Bus
 162  */
 163 #if 1
 164 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 165 #define CONFIG_FLASH_CFI_LEGACY
 166 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 167 #endif
 168
 169 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 170 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 171
 172 /* Window base at flash base */
 173 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 174                                 | BR_PS_16      /* 16 bit port */ \
 175                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 176                                 | BR_V)         /* valid */
 177 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 178                                 | OR_UPM_XAM \
 179                                 | OR_GPCM_CSNT \
 180                                 | OR_GPCM_ACS_DIV2 \
 181                                 | OR_GPCM_XACS \
 182                                 | OR_GPCM_SCY_15 \
 183                                 | OR_GPCM_TRLX_SET \
 184                                 | OR_GPCM_EHTR_SET)
 185
 186 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 187 #define CONFIG_SYS_MAX_FLASH_SECT       135
 188
 189 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 190 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 191
 192 /*
 193  * FPGA
 194  */
 195 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 196 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 197
 198 /* Window base at FPGA base */
 199 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 200                                 | BR_PS_16      /* 16 bit port */ \
 201                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 202                                 | BR_V)         /* valid */
 203 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 204                                 | OR_UPM_XAM \
 205                                 | OR_GPCM_CSNT \
 206                                 | OR_GPCM_ACS_DIV2 \
 207                                 | OR_GPCM_XACS \
 208                                 | OR_GPCM_SCY_15 \
 209                                 | OR_GPCM_TRLX_SET \
 210                                 | OR_GPCM_EHTR_SET)
 211
 212 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 213 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 214
 215 #define CONFIG_SYS_FPGA_COUNT           1
 216
 217 #define CONFIG_SYS_MCLINK_MAX           3
 218
 219 #define CONFIG_SYS_FPGA_PTR \
 220         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 221
 222 /*
 223  * Serial Port
 224  */
 225 #define CONFIG_SYS_NS16550_SERIAL
 226 #define CONFIG_SYS_NS16550_REG_SIZE     1
 227 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 228
 229 #define CONFIG_SYS_BAUDRATE_TABLE  \
 230         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 231
 232 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 233 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 234
 235 /* Pass open firmware flat tree */
 236
 237 /* I2C */
 238 #define CONFIG_SYS_I2C
 239 #define CONFIG_SYS_I2C_FSL
 240 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 241 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 242 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 243
 244 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 245 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 246
 247 #define CONFIG_SYS_I2C_IHS
 248 #define CONFIG_SYS_I2C_IHS_CH0
 249 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 250 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 251 #define CONFIG_SYS_I2C_IHS_CH1
 252 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 253 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 254 #define CONFIG_SYS_I2C_IHS_CH2
 255 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 256 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 257 #define CONFIG_SYS_I2C_IHS_CH3
 258 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 259 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 260
 261 #ifdef CONFIG_HRCON_DH
 262 #define CONFIG_SYS_I2C_IHS_DUAL
 263 #define CONFIG_SYS_I2C_IHS_CH0_1
 264 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 265 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 266 #define CONFIG_SYS_I2C_IHS_CH1_1
 267 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 268 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 269 #define CONFIG_SYS_I2C_IHS_CH2_1
 270 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 271 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 272 #define CONFIG_SYS_I2C_IHS_CH3_1
 273 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 274 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 275 #endif
 276
 277 /*
 278  * Software (bit-bang) I2C driver configuration
 279  */
 280 #define CONFIG_SYS_I2C_SOFT
 281 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 282 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 283 #define I2C_SOFT_DECLARATIONS2
 284 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 285 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 286 #define I2C_SOFT_DECLARATIONS3
 287 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 288 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 289 #define I2C_SOFT_DECLARATIONS4
 290 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 291 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 292 #define I2C_SOFT_DECLARATIONS5
 293 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 294 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 295 #define I2C_SOFT_DECLARATIONS6
 296 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 297 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 298 #define I2C_SOFT_DECLARATIONS7
 299 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 300 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 301 #define I2C_SOFT_DECLARATIONS8
 302 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 303 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 304
 305 #ifdef CONFIG_HRCON_DH
 306 #define I2C_SOFT_DECLARATIONS9
 307 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 308 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 309 #define I2C_SOFT_DECLARATIONS10
 310 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 311 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 312 #define I2C_SOFT_DECLARATIONS11
 313 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 314 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 315 #define I2C_SOFT_DECLARATIONS12
 316 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 317 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 318 #endif
 319
 320 #ifdef CONFIG_HRCON_DH
 321 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 322 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 323 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 324                                                   {12, 0x4c} }
 325 #else
 326 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 327 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 328 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 329                                                   {8, 0x4c} }
 330 #endif
 331
 332 #ifndef __ASSEMBLY__
 333 void fpga_gpio_set(unsigned int bus, int pin);
 334 void fpga_gpio_clear(unsigned int bus, int pin);
 335 int fpga_gpio_get(unsigned int bus, int pin);
 336 void fpga_control_set(unsigned int bus, int pin);
 337 void fpga_control_clear(unsigned int bus, int pin);
 338 #endif
 339
 340 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 341 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 342 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 343
 344 #ifdef CONFIG_HRCON_DH
 345 #define I2C_ACTIVE \
 346         do { \
 347                 if (I2C_ADAP_HWNR > 7) \
 348                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 349                 else \
 350                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 351         } while (0)
 352 #else
 353 #define I2C_ACTIVE      { }
 354 #endif
 355 #define I2C_TRISTATE    { }
 356 #define I2C_READ \
 357         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 358 #define I2C_SDA(bit) \
 359         do { \
 360                 if (bit) \
 361                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 362                 else \
 363                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 364         } while (0)
 365 #define I2C_SCL(bit) \
 366         do { \
 367                 if (bit) \
 368                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 369                 else \
 370                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 371         } while (0)
 372 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 373
 374 /*
 375  * Software (bit-bang) MII driver configuration
 376  */
 377 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 378 #define CONFIG_BITBANGMII_MULTI
 379
 380 /*
 381  * OSD Setup
 382  */
 383 #define CONFIG_SYS_OSD_SCREENS          1
 384 #define CONFIG_SYS_DP501_DIFFERENTIAL
 385 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 386
 387 #ifdef CONFIG_HRCON_DH
 388 #define CONFIG_SYS_OSD_DH
 389 #endif
 390
 391 /*
 392  * General PCI
 393  * Addresses are mapped 1-1.
 394  */
 395 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 396 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 397 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 398 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 399 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 400 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 401 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 402 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 403 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 404
 405 /* enable PCIE clock */
 406 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 407
 408 #define CONFIG_PCI_INDIRECT_BRIDGE
 409 #define CONFIG_PCIE
 410
 411 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 412 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 413
 414 /*
 415  * TSEC
 416  */
 417 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 418 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 419
 420 /*
 421  * TSEC ethernet configuration
 422  */
 423 #define CONFIG_TSEC1
 424 #define CONFIG_TSEC1_NAME       "eTSEC0"
 425 #define TSEC1_PHY_ADDR          1
 426 #define TSEC1_PHYIDX            0
 427 #define TSEC1_FLAGS             TSEC_GIGABIT
 428
 429 /* Options are: eTSEC[0-1] */
 430 #define CONFIG_ETHPRIME         "eTSEC0"
 431
 432 /*
 433  * Environment
 434  */
 435 #if 1
 436 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 437                                  CONFIG_SYS_MONITOR_LEN)
 438 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 439 #define CONFIG_ENV_SIZE         0x2000
 440 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 441 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 442 #else
 443 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 444 #endif
 445
 446 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 447 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 448
 449 /*
 450  * Command line configuration.
 451  */
 452
 453 /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 457 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 458
 459 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 460
 461 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 462
 463 /*
 464  * For booting Linux, the board info and command line data
 465  * have to be in the first 256 MB of memory, since this is
 466  * the maximum mapped by the Linux kernel during initialization.
 467  */
 468 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 469
 470 /*
 471  * Core HID Setup
 472  */
 473 #define CONFIG_SYS_HID0_INIT    0x000000000
 474 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 475                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 476                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 477 #define CONFIG_SYS_HID2         HID2_HBE
 478
 479 /*
 480  * Environment Configuration
 481  */
 482
 483 #define CONFIG_ENV_OVERWRITE
 484
 485 #if defined(CONFIG_TSEC_ENET)
 486 #define CONFIG_HAS_ETH0
 487 #endif
 488
 489 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 490
 491
 492 #define CONFIG_HOSTNAME         "hrcon"
 493 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 494 #define CONFIG_BOOTFILE         "uImage"
 495
 496 #define CONFIG_PREBOOT          /* enable preboot variable */
 497
 498 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 499         "netdev=eth0\0"                                                 \
 500         "consoledev=ttyS1\0"                                            \
 501         "u-boot=u-boot.bin\0"                                           \
 502         "kernel_addr=1000000\0"                                 \
 503         "fdt_addr=C00000\0"                                             \
 504         "fdtfile=hrcon.dtb\0"                           \
 505         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 506         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 507                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 508                 " +${filesize};cp.b ${fileaddr} "                       \
 509                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 510         "upd=run load update\0"                                         \
 511
 512 #define CONFIG_NFSBOOTCOMMAND                                           \
 513         "setenv bootargs root=/dev/nfs rw "                             \
 514         "nfsroot=$serverip:$rootpath "                                  \
 515         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 516         "console=$consoledev,$baudrate $othbootargs;"                   \
 517         "tftp ${kernel_addr} $bootfile;"                                \
 518         "tftp ${fdt_addr} $fdtfile;"                                    \
 519         "bootm ${kernel_addr} - ${fdt_addr}"
 520
 521 #define CONFIG_MMCBOOTCOMMAND                                           \
 522         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 523         "console=$consoledev,$baudrate $othbootargs;"                   \
 524         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 525         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 526         "bootm ${kernel_addr} - ${fdt_addr}"
 527
 528 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 529
 530 #endif  /* __CONFIG_H */