include/configs/hrcon.h

   1 /*
   2  * (C) Copyright 2014
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1 /* E300 family */
  16 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  17 #define CONFIG_MPC830x          1 /* MPC830x family */
  18 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  19 #define CONFIG_HRCON            1 /* HRCON board specific */
  20
  21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  22
  23 #define CONFIG_BOARD_EARLY_INIT_F
  24 #define CONFIG_BOARD_EARLY_INIT_R
  25 #define CONFIG_LAST_STAGE_INIT
  26
  27 #define CONFIG_FSL_ESDHC
  28 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  29
  30 #define CONFIG_GENERIC_MMC
  31 #define CONFIG_DOS_PARTITION
  32
  33 #define CONFIG_CMD_FPGAD
  34 #define CONFIG_CMD_IOLOOP
  35
  36 /*
  37  * System Clock Setup
  38  */
  39 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  40 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  41
  42 /*
  43  * Hardware Reset Configuration Word
  44  * if CLKIN is 66.66MHz, then
  45  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  46  * We choose the A type silicon as default, so the core is 400Mhz.
  47  */
  48 #define CONFIG_SYS_HRCW_LOW (\
  49         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  50         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  51         HRCWL_SVCOD_DIV_2 |\
  52         HRCWL_CSB_TO_CLKIN_4X1 |\
  53         HRCWL_CORE_TO_CSB_3X1)
  54 /*
  55  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  56  * in 8308's HRCWH according to the manual, but original Freescale's
  57  * code has them and I've expirienced some problems using the board
  58  * with BDI3000 attached when I've tried to set these bits to zero
  59  * (UART doesn't work after the 'reset run' command).
  60  */
  61 #define CONFIG_SYS_HRCW_HIGH (\
  62         HRCWH_PCI_HOST |\
  63         HRCWH_PCI1_ARBITER_ENABLE |\
  64         HRCWH_CORE_ENABLE |\
  65         HRCWH_FROM_0XFFF00100 |\
  66         HRCWH_BOOTSEQ_DISABLE |\
  67         HRCWH_SW_WATCHDOG_DISABLE |\
  68         HRCWH_ROM_LOC_LOCAL_16BIT |\
  69         HRCWH_RL_EXT_LEGACY |\
  70         HRCWH_TSEC1M_IN_RGMII |\
  71         HRCWH_TSEC2M_IN_RGMII |\
  72         HRCWH_BIG_ENDIAN)
  73
  74 /*
  75  * System IO Config
  76  */
  77 #define CONFIG_SYS_SICRH (\
  78         SICRH_ESDHC_A_SD |\
  79         SICRH_ESDHC_B_SD |\
  80         SICRH_ESDHC_C_SD |\
  81         SICRH_GPIO_A_GPIO |\
  82         SICRH_GPIO_B_GPIO |\
  83         SICRH_IEEE1588_A_GPIO |\
  84         SICRH_USB |\
  85         SICRH_GTM_GPIO |\
  86         SICRH_IEEE1588_B_GPIO |\
  87         SICRH_ETSEC2_GPIO |\
  88         SICRH_GPIOSEL_1 |\
  89         SICRH_TMROBI_V3P3 |\
  90         SICRH_TSOBI1_V2P5 |\
  91         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  92 #define CONFIG_SYS_SICRL (\
  93         SICRL_SPI_PF0 |\
  94         SICRL_UART_PF0 |\
  95         SICRL_IRQ_PF0 |\
  96         SICRL_I2C2_PF0 |\
  97         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  98
  99 /*
 100  * IMMR new address
 101  */
 102 #define CONFIG_SYS_IMMR         0xE0000000
 103
 104 /*
 105  * SERDES
 106  */
 107 #define CONFIG_FSL_SERDES
 108 #define CONFIG_FSL_SERDES1      0xe3000
 109
 110 /*
 111  * Arbiter Setup
 112  */
 113 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 114 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 115 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 116
 117 /*
 118  * DDR Setup
 119  */
 120 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 122 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 123 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 124 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 125                                 | DDRCDR_PZ_LOZ \
 126                                 | DDRCDR_NZ_LOZ \
 127                                 | DDRCDR_ODT \
 128                                 | DDRCDR_Q_DRN)
 129                                 /* 0x7b880001 */
 130 /*
 131  * Manually set up DDR parameters
 132  * consist of one chip NT5TU64M16HG from NANYA
 133  */
 134
 135 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 136
 137 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 138 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 139                                 | CSCONFIG_ODT_RD_NEVER \
 140                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 141                                 | CSCONFIG_BANK_BIT_3 \
 142                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 143                                 /* 0x80010102 */
 144 #define CONFIG_SYS_DDR_TIMING_3 0
 145 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 146                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 147                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 148                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 149                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 150                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 151                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 152                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 153                                 /* 0x00260802 */
 154 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 155                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 156                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 157                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 158                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 159                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 160                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 161                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 162                                 /* 0x26279222 */
 163 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 164                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 165                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 166                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 167                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 168                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 169                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 170                                 /* 0x021848c5 */
 171 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 172                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 173                                 /* 0x08240100 */
 174 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 175                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 176                                 | SDRAM_CFG_DBW_16)
 177                                 /* 0x43100000 */
 178
 179 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 180 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 181                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 182                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 183 #define CONFIG_SYS_DDR_MODE2            0x00000000
 184
 185 /*
 186  * Memory test
 187  */
 188 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 189 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 190
 191 /*
 192  * The reserved memory
 193  */
 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 195
 196 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 197 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 198
 199 /*
 200  * Initial RAM Base Address Setup
 201  */
 202 #define CONFIG_SYS_INIT_RAM_LOCK        1
 203 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 204 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 205 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 206         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 207
 208 /*
 209  * Local Bus Configuration & Clock Setup
 210  */
 211 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 212 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 213 #define CONFIG_SYS_LBC_LBCR             0x00040000
 214
 215 /*
 216  * FLASH on the Local Bus
 217  */
 218 #if 1
 219 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 220 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 221 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 222 #define CONFIG_FLASH_CFI_LEGACY
 223 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 224 #else
 225 #define CONFIG_SYS_NO_FLASH
 226 #endif
 227
 228 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 229 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 230 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 231
 232 /* Window base at flash base */
 233 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 234 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 235
 236 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 237                                 | BR_PS_16      /* 16 bit port */ \
 238                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 239                                 | BR_V)         /* valid */
 240 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 241                                 | OR_UPM_XAM \
 242                                 | OR_GPCM_CSNT \
 243                                 | OR_GPCM_ACS_DIV2 \
 244                                 | OR_GPCM_XACS \
 245                                 | OR_GPCM_SCY_15 \
 246                                 | OR_GPCM_TRLX_SET \
 247                                 | OR_GPCM_EHTR_SET)
 248
 249 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 250 #define CONFIG_SYS_MAX_FLASH_SECT       135
 251
 252 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 253 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 254
 255 /*
 256  * FPGA
 257  */
 258 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 259 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 260
 261 /* Window base at FPGA base */
 262 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 263 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 264
 265 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 266                                 | BR_PS_16      /* 16 bit port */ \
 267                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 268                                 | BR_V)         /* valid */
 269 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 270                                 | OR_UPM_XAM \
 271                                 | OR_GPCM_CSNT \
 272                                 | OR_GPCM_ACS_DIV2 \
 273                                 | OR_GPCM_XACS \
 274                                 | OR_GPCM_SCY_15 \
 275                                 | OR_GPCM_TRLX_SET \
 276                                 | OR_GPCM_EHTR_SET)
 277
 278 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 279 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 280
 281 #define CONFIG_SYS_FPGA_COUNT           1
 282
 283 #define CONFIG_SYS_MCLINK_MAX           3
 284
 285 #define CONFIG_SYS_FPGA_PTR \
 286         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 287
 288 /*
 289  * Serial Port
 290  */
 291 #define CONFIG_CONS_INDEX       2
 292 #define CONFIG_SYS_NS16550_SERIAL
 293 #define CONFIG_SYS_NS16550_REG_SIZE     1
 294 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 295
 296 #define CONFIG_SYS_BAUDRATE_TABLE  \
 297         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 298
 299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 301
 302 /* Pass open firmware flat tree */
 303
 304 /* I2C */
 305 #define CONFIG_SYS_I2C
 306 #define CONFIG_SYS_I2C_FSL
 307 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 308 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 309 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 310
 311 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 312 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 313
 314 #define CONFIG_SYS_I2C_IHS
 315 #define CONFIG_SYS_I2C_IHS_CH0
 316 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 317 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 318 #define CONFIG_SYS_I2C_IHS_CH1
 319 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 320 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 321 #define CONFIG_SYS_I2C_IHS_CH2
 322 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 323 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 324 #define CONFIG_SYS_I2C_IHS_CH3
 325 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 326 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 327
 328 #ifdef CONFIG_HRCON_DH
 329 #define CONFIG_SYS_I2C_IHS_DUAL
 330 #define CONFIG_SYS_I2C_IHS_CH0_1
 331 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 332 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 333 #define CONFIG_SYS_I2C_IHS_CH1_1
 334 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 335 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 336 #define CONFIG_SYS_I2C_IHS_CH2_1
 337 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 338 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 339 #define CONFIG_SYS_I2C_IHS_CH3_1
 340 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 341 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 342 #endif
 343
 344 /*
 345  * Software (bit-bang) I2C driver configuration
 346  */
 347 #define CONFIG_SYS_I2C_SOFT
 348 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 349 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 350 #define I2C_SOFT_DECLARATIONS2
 351 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 353 #define I2C_SOFT_DECLARATIONS3
 354 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 356 #define I2C_SOFT_DECLARATIONS4
 357 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 359 #define I2C_SOFT_DECLARATIONS5
 360 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 361 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 362 #define I2C_SOFT_DECLARATIONS6
 363 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 364 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 365 #define I2C_SOFT_DECLARATIONS7
 366 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 367 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 368 #define I2C_SOFT_DECLARATIONS8
 369 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 370 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 371
 372 #ifdef CONFIG_HRCON_DH
 373 #define I2C_SOFT_DECLARATIONS9
 374 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 375 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 376 #define I2C_SOFT_DECLARATIONS10
 377 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 378 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 379 #define I2C_SOFT_DECLARATIONS11
 380 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 381 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 382 #define I2C_SOFT_DECLARATIONS12
 383 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 384 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 385 #endif
 386
 387 #ifdef CONFIG_HRCON_DH
 388 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 389 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 390 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 391                                                   {12, 0x4c} }
 392 #else
 393 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 394 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 395 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 396                                                   {8, 0x4c} }
 397 #endif
 398
 399 #ifndef __ASSEMBLY__
 400 void fpga_gpio_set(unsigned int bus, int pin);
 401 void fpga_gpio_clear(unsigned int bus, int pin);
 402 int fpga_gpio_get(unsigned int bus, int pin);
 403 void fpga_control_set(unsigned int bus, int pin);
 404 void fpga_control_clear(unsigned int bus, int pin);
 405 #endif
 406
 407 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 408 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 409 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 410
 411 #ifdef CONFIG_HRCON_DH
 412 #define I2C_ACTIVE \
 413         do { \
 414                 if (I2C_ADAP_HWNR > 7) \
 415                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 416                 else \
 417                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 418         } while (0)
 419 #else
 420 #define I2C_ACTIVE      { }
 421 #endif
 422 #define I2C_TRISTATE    { }
 423 #define I2C_READ \
 424         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 425 #define I2C_SDA(bit) \
 426         do { \
 427                 if (bit) \
 428                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 429                 else \
 430                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 431         } while (0)
 432 #define I2C_SCL(bit) \
 433         do { \
 434                 if (bit) \
 435                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 436                 else \
 437                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 438         } while (0)
 439 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 440
 441 /*
 442  * Software (bit-bang) MII driver configuration
 443  */
 444 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 445 #define CONFIG_BITBANGMII_MULTI
 446
 447 /*
 448  * OSD Setup
 449  */
 450 #define CONFIG_SYS_OSD_SCREENS          1
 451 #define CONFIG_SYS_DP501_DIFFERENTIAL
 452 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 453
 454 #ifdef CONFIG_HRCON_DH
 455 #define CONFIG_SYS_OSD_DH
 456 #endif
 457
 458 /*
 459  * General PCI
 460  * Addresses are mapped 1-1.
 461  */
 462 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 463 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 464 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 465 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 466 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 467 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 468 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 469 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 470 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 471
 472 /* enable PCIE clock */
 473 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 474
 475 #define CONFIG_PCI_INDIRECT_BRIDGE
 476 #define CONFIG_PCIE
 477
 478 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 479 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 480
 481 /*
 482  * TSEC
 483  */
 484 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 485 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 486 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 487
 488 /*
 489  * TSEC ethernet configuration
 490  */
 491 #define CONFIG_MII              1 /* MII PHY management */
 492 #define CONFIG_TSEC1
 493 #define CONFIG_TSEC1_NAME       "eTSEC0"
 494 #define TSEC1_PHY_ADDR          1
 495 #define TSEC1_PHYIDX            0
 496 #define TSEC1_FLAGS             TSEC_GIGABIT
 497
 498 /* Options are: eTSEC[0-1] */
 499 #define CONFIG_ETHPRIME         "eTSEC0"
 500
 501 /*
 502  * Environment
 503  */
 504 #if 1
 505 #define CONFIG_ENV_IS_IN_FLASH  1
 506 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 507                                  CONFIG_SYS_MONITOR_LEN)
 508 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 509 #define CONFIG_ENV_SIZE         0x2000
 510 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 511 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 512 #else
 513 #define CONFIG_ENV_IS_NOWHERE
 514 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 515 #endif
 516
 517 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 518 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 519
 520 /*
 521  * Command line configuration.
 522  */
 523 #define CONFIG_CMD_PCI
 524
 525 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 526 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 527
 528 /*
 529  * Miscellaneous configurable options
 530  */
 531 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 532 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 533 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 534
 535 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 536
 537 /* Print Buffer Size */
 538 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 539 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 540 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 541
 542 /*
 543  * For booting Linux, the board info and command line data
 544  * have to be in the first 256 MB of memory, since this is
 545  * the maximum mapped by the Linux kernel during initialization.
 546  */
 547 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 548
 549 /*
 550  * Core HID Setup
 551  */
 552 #define CONFIG_SYS_HID0_INIT    0x000000000
 553 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 554                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 555                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 556 #define CONFIG_SYS_HID2         HID2_HBE
 557
 558 /*
 559  * MMU Setup
 560  */
 561
 562 /* DDR: cache cacheable */
 563 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 564                                         BATL_MEMCOHERENCE)
 565 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 566                                         BATU_VS | BATU_VP)
 567 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 568 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 569
 570 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 571 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 572                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 573 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 574                                         BATU_VP)
 575 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 576 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 577
 578 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 579 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 580                                         BATL_MEMCOHERENCE)
 581 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 582                                         BATU_VS | BATU_VP)
 583 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 584                                         BATL_CACHEINHIBIT | \
 585                                         BATL_GUARDEDSTORAGE)
 586 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 587
 588 /* Stack in dcache: cacheable, no memory coherence */
 589 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 590 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 591                                         BATU_VS | BATU_VP)
 592 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 593 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 594
 595 /*
 596  * Environment Configuration
 597  */
 598
 599 #define CONFIG_ENV_OVERWRITE
 600
 601 #if defined(CONFIG_TSEC_ENET)
 602 #define CONFIG_HAS_ETH0
 603 #endif
 604
 605 #define CONFIG_BAUDRATE 115200
 606
 607 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 608
 609
 610 #define CONFIG_HOSTNAME         hrcon
 611 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 612 #define CONFIG_BOOTFILE         "uImage"
 613
 614 #define CONFIG_PREBOOT          /* enable preboot variable */
 615
 616 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 617         "netdev=eth0\0"                                                 \
 618         "consoledev=ttyS1\0"                                            \
 619         "u-boot=u-boot.bin\0"                                           \
 620         "kernel_addr=1000000\0"                                 \
 621         "fdt_addr=C00000\0"                                             \
 622         "fdtfile=hrcon.dtb\0"                           \
 623         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 624         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 625                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 626                 " +${filesize};cp.b ${fileaddr} "                       \
 627                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 628         "upd=run load update\0"                                         \
 629
 630 #define CONFIG_NFSBOOTCOMMAND                                           \
 631         "setenv bootargs root=/dev/nfs rw "                             \
 632         "nfsroot=$serverip:$rootpath "                                  \
 633         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 634         "console=$consoledev,$baudrate $othbootargs;"                   \
 635         "tftp ${kernel_addr} $bootfile;"                                \
 636         "tftp ${fdt_addr} $fdtfile;"                                    \
 637         "bootm ${kernel_addr} - ${fdt_addr}"
 638
 639 #define CONFIG_MMCBOOTCOMMAND                                           \
 640         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 641         "console=$consoledev,$baudrate $othbootargs;"                   \
 642         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 643         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 644         "bootm ${kernel_addr} - ${fdt_addr}"
 645
 646 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 647
 648 #endif  /* __CONFIG_H */