1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
21 #define CONFIG_FSL_SERDES
22 #define CONFIG_FSL_SERDES1 0xe3000
27 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
28 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
29 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
30 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
31 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
38 * Manually set up DDR parameters
39 * consist of one chip NT5TU64M16HG from NANYA
42 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
44 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
45 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
46 | CSCONFIG_ODT_RD_NEVER \
47 | CSCONFIG_ODT_WR_ONLY_CURRENT \
48 | CSCONFIG_BANK_BIT_3 \
49 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
51 #define CONFIG_SYS_DDR_TIMING_3 0
52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
53 | (0 << TIMING_CFG0_WRT_SHIFT) \
54 | (0 << TIMING_CFG0_RRT_SHIFT) \
55 | (0 << TIMING_CFG0_WWT_SHIFT) \
56 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
57 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
58 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
59 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
62 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
63 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
64 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
65 | (9 << TIMING_CFG1_REFREC_SHIFT) \
66 | (2 << TIMING_CFG1_WRREC_SHIFT) \
67 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
68 | (2 << TIMING_CFG1_WRTORD_SHIFT))
70 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
71 | (4 << TIMING_CFG2_CPO_SHIFT) \
72 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
73 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
74 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
75 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
76 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
78 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
79 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
81 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
82 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
86 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
87 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
88 | (0x0242 << SDRAM_MODE_SD_SHIFT))
89 /* ODT 150ohm CL=4, AL=0 on SDRAM */
90 #define CONFIG_SYS_DDR_MODE2 0x00000000
95 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
96 #define CONFIG_SYS_MEMTEST_END 0x07f00000
101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
103 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
104 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
107 * Initial RAM Base Address Setup
109 #define CONFIG_SYS_INIT_RAM_LOCK 1
110 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
111 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
112 #define CONFIG_SYS_GBL_DATA_OFFSET \
113 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
116 * Local Bus Configuration & Clock Setup
118 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
119 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
120 #define CONFIG_SYS_LBC_LBCR 0x00040000
123 * FLASH on the Local Bus
126 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
127 #define CONFIG_FLASH_CFI_LEGACY
128 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
131 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
132 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
135 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
136 #define CONFIG_SYS_MAX_FLASH_SECT 135
138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
145 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
148 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
149 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
151 #define CONFIG_SYS_FPGA_COUNT 1
153 #define CONFIG_SYS_MCLINK_MAX 3
155 #define CONFIG_SYS_FPGA_PTR \
156 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
161 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE 1
163 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
165 #define CONFIG_SYS_BAUDRATE_TABLE \
166 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
171 /* Pass open firmware flat tree */
174 #define CONFIG_SYS_I2C
175 #define CONFIG_SYS_I2C_FSL
176 #define CONFIG_SYS_FSL_I2C_SPEED 400000
177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
180 #define CONFIG_PCA953X /* NXP PCA9554 */
181 #define CONFIG_PCA9698 /* NXP PCA9698 */
183 #define CONFIG_SYS_I2C_IHS
184 #define CONFIG_SYS_I2C_IHS_CH0
185 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
186 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
187 #define CONFIG_SYS_I2C_IHS_CH1
188 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
189 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
190 #define CONFIG_SYS_I2C_IHS_CH2
191 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
192 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
193 #define CONFIG_SYS_I2C_IHS_CH3
194 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
195 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
197 #ifdef CONFIG_HRCON_DH
198 #define CONFIG_SYS_I2C_IHS_DUAL
199 #define CONFIG_SYS_I2C_IHS_CH0_1
200 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
201 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
202 #define CONFIG_SYS_I2C_IHS_CH1_1
203 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
204 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
205 #define CONFIG_SYS_I2C_IHS_CH2_1
206 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
207 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
208 #define CONFIG_SYS_I2C_IHS_CH3_1
209 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
210 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
214 * Software (bit-bang) I2C driver configuration
216 #define CONFIG_SYS_I2C_SOFT
217 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
218 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
219 #define I2C_SOFT_DECLARATIONS2
220 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
221 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
222 #define I2C_SOFT_DECLARATIONS3
223 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
224 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
225 #define I2C_SOFT_DECLARATIONS4
226 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
227 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
228 #define I2C_SOFT_DECLARATIONS5
229 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
230 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
231 #define I2C_SOFT_DECLARATIONS6
232 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
233 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
234 #define I2C_SOFT_DECLARATIONS7
235 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
236 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
237 #define I2C_SOFT_DECLARATIONS8
238 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
239 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
241 #ifdef CONFIG_HRCON_DH
242 #define I2C_SOFT_DECLARATIONS9
243 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
244 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
245 #define I2C_SOFT_DECLARATIONS10
246 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
247 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
248 #define I2C_SOFT_DECLARATIONS11
249 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
250 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
251 #define I2C_SOFT_DECLARATIONS12
252 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
253 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
256 #ifdef CONFIG_HRCON_DH
257 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
258 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
259 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
262 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
263 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
264 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
269 void fpga_gpio_set(unsigned int bus, int pin);
270 void fpga_gpio_clear(unsigned int bus, int pin);
271 int fpga_gpio_get(unsigned int bus, int pin);
272 void fpga_control_set(unsigned int bus, int pin);
273 void fpga_control_clear(unsigned int bus, int pin);
276 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
277 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
278 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
280 #ifdef CONFIG_HRCON_DH
283 if (I2C_ADAP_HWNR > 7) \
284 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
286 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
289 #define I2C_ACTIVE { }
291 #define I2C_TRISTATE { }
293 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
294 #define I2C_SDA(bit) \
297 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
299 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
301 #define I2C_SCL(bit) \
304 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
306 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
308 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
311 * Software (bit-bang) MII driver configuration
313 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
314 #define CONFIG_BITBANGMII_MULTI
319 #define CONFIG_SYS_OSD_SCREENS 1
320 #define CONFIG_SYS_DP501_DIFFERENTIAL
321 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
323 #ifdef CONFIG_HRCON_DH
324 #define CONFIG_SYS_OSD_DH
329 * Addresses are mapped 1-1.
331 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
332 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
333 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
334 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
335 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
336 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
337 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
338 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
339 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
341 /* enable PCIE clock */
342 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
344 #define CONFIG_PCI_INDIRECT_BRIDGE
347 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
348 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
353 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
354 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
357 * TSEC ethernet configuration
360 #define CONFIG_TSEC1_NAME "eTSEC0"
361 #define TSEC1_PHY_ADDR 1
362 #define TSEC1_PHYIDX 0
363 #define TSEC1_FLAGS TSEC_GIGABIT
365 /* Options are: eTSEC[0-1] */
366 #define CONFIG_ETHPRIME "eTSEC0"
372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
373 CONFIG_SYS_MONITOR_LEN)
374 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
375 #define CONFIG_ENV_SIZE 0x2000
376 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
377 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
379 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
382 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
383 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
386 * Command line configuration.
390 * Miscellaneous configurable options
392 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
393 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
395 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
397 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
400 * For booting Linux, the board info and command line data
401 * have to be in the first 256 MB of memory, since this is
402 * the maximum mapped by the Linux kernel during initialization.
404 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
407 * Environment Configuration
410 #define CONFIG_ENV_OVERWRITE
412 #if defined(CONFIG_TSEC_ENET)
413 #define CONFIG_HAS_ETH0
416 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
419 #define CONFIG_HOSTNAME "hrcon"
420 #define CONFIG_ROOTPATH "/opt/nfsroot"
421 #define CONFIG_BOOTFILE "uImage"
423 #define CONFIG_PREBOOT /* enable preboot variable */
425 #define CONFIG_EXTRA_ENV_SETTINGS \
427 "consoledev=ttyS1\0" \
428 "u-boot=u-boot.bin\0" \
429 "kernel_addr=1000000\0" \
430 "fdt_addr=C00000\0" \
431 "fdtfile=hrcon.dtb\0" \
432 "load=tftp ${loadaddr} ${u-boot}\0" \
433 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
434 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
435 " +${filesize};cp.b ${fileaddr} " \
436 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
437 "upd=run load update\0" \
439 #define CONFIG_NFSBOOTCOMMAND \
440 "setenv bootargs root=/dev/nfs rw " \
441 "nfsroot=$serverip:$rootpath " \
442 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
443 "console=$consoledev,$baudrate $othbootargs;" \
444 "tftp ${kernel_addr} $bootfile;" \
445 "tftp ${fdt_addr} $fdtfile;" \
446 "bootm ${kernel_addr} - ${fdt_addr}"
448 #define CONFIG_MMCBOOTCOMMAND \
449 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
450 "console=$consoledev,$baudrate $othbootargs;" \
451 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
452 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
453 "bootm ${kernel_addr} - ${fdt_addr}"
455 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
457 #endif /* __CONFIG_H */