include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  16 #define CONFIG_MPC830x          1 /* MPC830x family */
  17 #define CONFIG_MPC8308          1 /* MPC8308 CPU specific */
  18 #define CONFIG_HRCON            1 /* HRCON board specific */
  19
  20 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  21
  22 /*
  23  * System Clock Setup
  24  */
  25 #define CONFIG_83XX_CLKIN       33333333 /* in Hz */
  26 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  27
  28 /*
  29  * Hardware Reset Configuration Word
  30  * if CLKIN is 66.66MHz, then
  31  * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
  32  * We choose the A type silicon as default, so the core is 400Mhz.
  33  */
  34 #define CONFIG_SYS_HRCW_LOW (\
  35         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  36         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  37         HRCWL_SVCOD_DIV_2 |\
  38         HRCWL_CSB_TO_CLKIN_4X1 |\
  39         HRCWL_CORE_TO_CSB_3X1)
  40 /*
  41  * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
  42  * in 8308's HRCWH according to the manual, but original Freescale's
  43  * code has them and I've expirienced some problems using the board
  44  * with BDI3000 attached when I've tried to set these bits to zero
  45  * (UART doesn't work after the 'reset run' command).
  46  */
  47 #define CONFIG_SYS_HRCW_HIGH (\
  48         HRCWH_PCI_HOST |\
  49         HRCWH_PCI1_ARBITER_ENABLE |\
  50         HRCWH_CORE_ENABLE |\
  51         HRCWH_FROM_0XFFF00100 |\
  52         HRCWH_BOOTSEQ_DISABLE |\
  53         HRCWH_SW_WATCHDOG_DISABLE |\
  54         HRCWH_ROM_LOC_LOCAL_16BIT |\
  55         HRCWH_RL_EXT_LEGACY |\
  56         HRCWH_TSEC1M_IN_RGMII |\
  57         HRCWH_TSEC2M_IN_RGMII |\
  58         HRCWH_BIG_ENDIAN)
  59
  60 /*
  61  * System IO Config
  62  */
  63 #define CONFIG_SYS_SICRH (\
  64         SICRH_ESDHC_A_SD |\
  65         SICRH_ESDHC_B_SD |\
  66         SICRH_ESDHC_C_SD |\
  67         SICRH_GPIO_A_GPIO |\
  68         SICRH_GPIO_B_GPIO |\
  69         SICRH_IEEE1588_A_GPIO |\
  70         SICRH_USB |\
  71         SICRH_GTM_GPIO |\
  72         SICRH_IEEE1588_B_GPIO |\
  73         SICRH_ETSEC2_GPIO |\
  74         SICRH_GPIOSEL_1 |\
  75         SICRH_TMROBI_V3P3 |\
  76         SICRH_TSOBI1_V2P5 |\
  77         SICRH_TSOBI2_V2P5)      /* 0x0037f103 */
  78 #define CONFIG_SYS_SICRL (\
  79         SICRL_SPI_PF0 |\
  80         SICRL_UART_PF0 |\
  81         SICRL_IRQ_PF0 |\
  82         SICRL_I2C2_PF0 |\
  83         SICRL_ETSEC1_GTX_CLK125)        /* 0x00000000 */
  84
  85 /*
  86  * IMMR new address
  87  */
  88 #define CONFIG_SYS_IMMR         0xE0000000
  89
  90 /*
  91  * SERDES
  92  */
  93 #define CONFIG_FSL_SERDES
  94 #define CONFIG_FSL_SERDES1      0xe3000
  95
  96 /*
  97  * Arbiter Setup
  98  */
  99 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
 100 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
 101 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
 102
 103 /*
 104  * DDR Setup
 105  */
 106 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 107 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 110 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 111                                 | DDRCDR_PZ_LOZ \
 112                                 | DDRCDR_NZ_LOZ \
 113                                 | DDRCDR_ODT \
 114                                 | DDRCDR_Q_DRN)
 115                                 /* 0x7b880001 */
 116 /*
 117  * Manually set up DDR parameters
 118  * consist of one chip NT5TU64M16HG from NANYA
 119  */
 120
 121 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 122
 123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 124 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 125                                 | CSCONFIG_ODT_RD_NEVER \
 126                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 127                                 | CSCONFIG_BANK_BIT_3 \
 128                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 129                                 /* 0x80010102 */
 130 #define CONFIG_SYS_DDR_TIMING_3 0
 131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 132                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 133                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 134                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 135                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 136                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 137                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 138                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 139                                 /* 0x00260802 */
 140 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 141                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 142                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 143                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 144                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
 145                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 146                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 147                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 148                                 /* 0x26279222 */
 149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 150                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 151                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 152                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 153                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 154                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 155                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 156                                 /* 0x021848c5 */
 157 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
 158                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 159                                 /* 0x08240100 */
 160 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 161                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 162                                 | SDRAM_CFG_DBW_16)
 163                                 /* 0x43100000 */
 164
 165 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 166 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
 167                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
 168                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
 169 #define CONFIG_SYS_DDR_MODE2            0x00000000
 170
 171 /*
 172  * Memory test
 173  */
 174 #define CONFIG_SYS_MEMTEST_START        0x00001000 /* memtest region */
 175 #define CONFIG_SYS_MEMTEST_END          0x07f00000
 176
 177 /*
 178  * The reserved memory
 179  */
 180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 181
 182 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 183 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 184
 185 /*
 186  * Initial RAM Base Address Setup
 187  */
 188 #define CONFIG_SYS_INIT_RAM_LOCK        1
 189 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 190 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 191 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 192         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 193
 194 /*
 195  * Local Bus Configuration & Clock Setup
 196  */
 197 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 198 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 199 #define CONFIG_SYS_LBC_LBCR             0x00040000
 200
 201 /*
 202  * FLASH on the Local Bus
 203  */
 204 #if 1
 205 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 206 #define CONFIG_FLASH_CFI_LEGACY
 207 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 208 #endif
 209
 210 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 211 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 212
 213 /* Window base at flash base */
 214 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 215 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 216
 217 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 218                                 | BR_PS_16      /* 16 bit port */ \
 219                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 220                                 | BR_V)         /* valid */
 221 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 222                                 | OR_UPM_XAM \
 223                                 | OR_GPCM_CSNT \
 224                                 | OR_GPCM_ACS_DIV2 \
 225                                 | OR_GPCM_XACS \
 226                                 | OR_GPCM_SCY_15 \
 227                                 | OR_GPCM_TRLX_SET \
 228                                 | OR_GPCM_EHTR_SET)
 229
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 231 #define CONFIG_SYS_MAX_FLASH_SECT       135
 232
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 235
 236 /*
 237  * FPGA
 238  */
 239 #define CONFIG_SYS_FPGA0_BASE           0xE0600000
 240 #define CONFIG_SYS_FPGA0_SIZE           1 /* FPGA size is 1M */
 241
 242 /* Window base at FPGA base */
 243 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA0_BASE
 244 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_1MB)
 245
 246 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FPGA0_BASE \
 247                                 | BR_PS_16      /* 16 bit port */ \
 248                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 249                                 | BR_V)         /* valid */
 250 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
 251                                 | OR_UPM_XAM \
 252                                 | OR_GPCM_CSNT \
 253                                 | OR_GPCM_ACS_DIV2 \
 254                                 | OR_GPCM_XACS \
 255                                 | OR_GPCM_SCY_15 \
 256                                 | OR_GPCM_TRLX_SET \
 257                                 | OR_GPCM_EHTR_SET)
 258
 259 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 260 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 261
 262 #define CONFIG_SYS_FPGA_COUNT           1
 263
 264 #define CONFIG_SYS_MCLINK_MAX           3
 265
 266 #define CONFIG_SYS_FPGA_PTR \
 267         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 268
 269 /*
 270  * Serial Port
 271  */
 272 #define CONFIG_SYS_NS16550_SERIAL
 273 #define CONFIG_SYS_NS16550_REG_SIZE     1
 274 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 275
 276 #define CONFIG_SYS_BAUDRATE_TABLE  \
 277         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 278
 279 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 280 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 281
 282 /* Pass open firmware flat tree */
 283
 284 /* I2C */
 285 #define CONFIG_SYS_I2C
 286 #define CONFIG_SYS_I2C_FSL
 287 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 288 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 289 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 290
 291 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 292 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 293
 294 #define CONFIG_SYS_I2C_IHS
 295 #define CONFIG_SYS_I2C_IHS_CH0
 296 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 297 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 298 #define CONFIG_SYS_I2C_IHS_CH1
 299 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 300 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 301 #define CONFIG_SYS_I2C_IHS_CH2
 302 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 303 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 304 #define CONFIG_SYS_I2C_IHS_CH3
 305 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 306 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 307
 308 #ifdef CONFIG_HRCON_DH
 309 #define CONFIG_SYS_I2C_IHS_DUAL
 310 #define CONFIG_SYS_I2C_IHS_CH0_1
 311 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 312 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 313 #define CONFIG_SYS_I2C_IHS_CH1_1
 314 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 315 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 316 #define CONFIG_SYS_I2C_IHS_CH2_1
 317 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 318 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 319 #define CONFIG_SYS_I2C_IHS_CH3_1
 320 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 321 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 322 #endif
 323
 324 /*
 325  * Software (bit-bang) I2C driver configuration
 326  */
 327 #define CONFIG_SYS_I2C_SOFT
 328 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 329 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 330 #define I2C_SOFT_DECLARATIONS2
 331 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 332 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 333 #define I2C_SOFT_DECLARATIONS3
 334 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 335 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 336 #define I2C_SOFT_DECLARATIONS4
 337 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 338 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 339 #define I2C_SOFT_DECLARATIONS5
 340 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 341 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 342 #define I2C_SOFT_DECLARATIONS6
 343 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 344 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 345 #define I2C_SOFT_DECLARATIONS7
 346 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 347 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 348 #define I2C_SOFT_DECLARATIONS8
 349 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 350 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 351
 352 #ifdef CONFIG_HRCON_DH
 353 #define I2C_SOFT_DECLARATIONS9
 354 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 356 #define I2C_SOFT_DECLARATIONS10
 357 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 359 #define I2C_SOFT_DECLARATIONS11
 360 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 361 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 362 #define I2C_SOFT_DECLARATIONS12
 363 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 364 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 365 #endif
 366
 367 #ifdef CONFIG_HRCON_DH
 368 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 369 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 370 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 371                                                   {12, 0x4c} }
 372 #else
 373 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 374 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 375 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 376                                                   {8, 0x4c} }
 377 #endif
 378
 379 #ifndef __ASSEMBLY__
 380 void fpga_gpio_set(unsigned int bus, int pin);
 381 void fpga_gpio_clear(unsigned int bus, int pin);
 382 int fpga_gpio_get(unsigned int bus, int pin);
 383 void fpga_control_set(unsigned int bus, int pin);
 384 void fpga_control_clear(unsigned int bus, int pin);
 385 #endif
 386
 387 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 388 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 389 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 390
 391 #ifdef CONFIG_HRCON_DH
 392 #define I2C_ACTIVE \
 393         do { \
 394                 if (I2C_ADAP_HWNR > 7) \
 395                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 396                 else \
 397                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 398         } while (0)
 399 #else
 400 #define I2C_ACTIVE      { }
 401 #endif
 402 #define I2C_TRISTATE    { }
 403 #define I2C_READ \
 404         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 405 #define I2C_SDA(bit) \
 406         do { \
 407                 if (bit) \
 408                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 409                 else \
 410                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 411         } while (0)
 412 #define I2C_SCL(bit) \
 413         do { \
 414                 if (bit) \
 415                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 416                 else \
 417                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 418         } while (0)
 419 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 420
 421 /*
 422  * Software (bit-bang) MII driver configuration
 423  */
 424 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 425 #define CONFIG_BITBANGMII_MULTI
 426
 427 /*
 428  * OSD Setup
 429  */
 430 #define CONFIG_SYS_OSD_SCREENS          1
 431 #define CONFIG_SYS_DP501_DIFFERENTIAL
 432 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 433
 434 #ifdef CONFIG_HRCON_DH
 435 #define CONFIG_SYS_OSD_DH
 436 #endif
 437
 438 /*
 439  * General PCI
 440  * Addresses are mapped 1-1.
 441  */
 442 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 443 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 444 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 445 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 446 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 447 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 448 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 449 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 450 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 451
 452 /* enable PCIE clock */
 453 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 454
 455 #define CONFIG_PCI_INDIRECT_BRIDGE
 456 #define CONFIG_PCIE
 457
 458 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 459 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 460
 461 /*
 462  * TSEC
 463  */
 464 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 465 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 466
 467 /*
 468  * TSEC ethernet configuration
 469  */
 470 #define CONFIG_TSEC1
 471 #define CONFIG_TSEC1_NAME       "eTSEC0"
 472 #define TSEC1_PHY_ADDR          1
 473 #define TSEC1_PHYIDX            0
 474 #define TSEC1_FLAGS             TSEC_GIGABIT
 475
 476 /* Options are: eTSEC[0-1] */
 477 #define CONFIG_ETHPRIME         "eTSEC0"
 478
 479 /*
 480  * Environment
 481  */
 482 #if 1
 483 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 484                                  CONFIG_SYS_MONITOR_LEN)
 485 #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 486 #define CONFIG_ENV_SIZE         0x2000
 487 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 488 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 489 #else
 490 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 491 #endif
 492
 493 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 494 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 495
 496 /*
 497  * Command line configuration.
 498  */
 499
 500 /*
 501  * Miscellaneous configurable options
 502  */
 503 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 504 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 505
 506 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 507
 508 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 509
 510 /*
 511  * For booting Linux, the board info and command line data
 512  * have to be in the first 256 MB of memory, since this is
 513  * the maximum mapped by the Linux kernel during initialization.
 514  */
 515 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 516
 517 /*
 518  * Core HID Setup
 519  */
 520 #define CONFIG_SYS_HID0_INIT    0x000000000
 521 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 522                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 523                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 524 #define CONFIG_SYS_HID2         HID2_HBE
 525
 526 /*
 527  * MMU Setup
 528  */
 529
 530 /* DDR: cache cacheable */
 531 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 532                                         BATL_MEMCOHERENCE)
 533 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
 534                                         BATU_VS | BATU_VP)
 535 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 536 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 537
 538 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
 539 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 540                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 541 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
 542                                         BATU_VP)
 543 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 544 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 545
 546 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 547 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 548                                         BATL_MEMCOHERENCE)
 549 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
 550                                         BATU_VS | BATU_VP)
 551 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 552                                         BATL_CACHEINHIBIT | \
 553                                         BATL_GUARDEDSTORAGE)
 554 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 555
 556 /* Stack in dcache: cacheable, no memory coherence */
 557 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 558 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 559                                         BATU_VS | BATU_VP)
 560 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 561 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 562
 563 /*
 564  * Environment Configuration
 565  */
 566
 567 #define CONFIG_ENV_OVERWRITE
 568
 569 #if defined(CONFIG_TSEC_ENET)
 570 #define CONFIG_HAS_ETH0
 571 #endif
 572
 573 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 574
 575
 576 #define CONFIG_HOSTNAME         "hrcon"
 577 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 578 #define CONFIG_BOOTFILE         "uImage"
 579
 580 #define CONFIG_PREBOOT          /* enable preboot variable */
 581
 582 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 583         "netdev=eth0\0"                                                 \
 584         "consoledev=ttyS1\0"                                            \
 585         "u-boot=u-boot.bin\0"                                           \
 586         "kernel_addr=1000000\0"                                 \
 587         "fdt_addr=C00000\0"                                             \
 588         "fdtfile=hrcon.dtb\0"                           \
 589         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 590         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 591                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 592                 " +${filesize};cp.b ${fileaddr} "                       \
 593                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 594         "upd=run load update\0"                                         \
 595
 596 #define CONFIG_NFSBOOTCOMMAND                                           \
 597         "setenv bootargs root=/dev/nfs rw "                             \
 598         "nfsroot=$serverip:$rootpath "                                  \
 599         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 600         "console=$consoledev,$baudrate $othbootargs;"                   \
 601         "tftp ${kernel_addr} $bootfile;"                                \
 602         "tftp ${fdt_addr} $fdtfile;"                                    \
 603         "bootm ${kernel_addr} - ${fdt_addr}"
 604
 605 #define CONFIG_MMCBOOTCOMMAND                                           \
 606         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 607         "console=$consoledev,$baudrate $othbootargs;"                   \
 608         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 609         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 610         "bootm ${kernel_addr} - ${fdt_addr}"
 611
 612 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 613
 614 #endif  /* __CONFIG_H */