1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Calxeda, Inc.
9 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)
11 #define CONFIG_SYS_TIMER_RATE (150000000/256)
12 #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
13 #define CONFIG_SYS_TIMER_COUNTS_DOWN
16 * Size of malloc() pool
18 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
20 #define CONFIG_PL011_CLOCK 150000000
21 #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
23 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
25 #define CONFIG_SCSI_AHCI_PLAT
26 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
27 #define CONFIG_SYS_SCSI_MAX_LUN 1
28 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
29 CONFIG_SYS_SCSI_MAX_LUN)
31 #define CONFIG_CALXEDA_XGMAC
34 * Command line configuration.
37 #define CONFIG_BOOT_RETRY_TIME -1
38 #define CONFIG_RESET_TO_RETRY
41 * Miscellaneous configurable options
43 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
44 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
46 #define CONFIG_SYS_LOAD_ADDR 0x800000
47 #define CONFIG_SYS_64BIT_LBA
49 /*-----------------------------------------------------------------------
51 * The DRAM is already setup, so do not touch the DT node later.
53 #define PHYS_SDRAM_1_SIZE (4089 << 20)
54 #define CONFIG_SYS_MEMTEST_START 0x100000
55 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
57 /* Environment data setup
59 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
60 #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
61 #define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */
62 #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
64 #define CONFIG_SYS_SDRAM_BASE 0x00000000
65 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000
66 #define CONFIG_SKIP_LOWLEVEL_INIT