2 * Copyright 2010-2011 Calxeda, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_SYS_DCACHE_OFF
12 #define CONFIG_SYS_BOOTMAPSZ (16 << 20)
14 #define CONFIG_SYS_TIMER_RATE (150000000/256)
15 #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
16 #define CONFIG_SYS_TIMER_COUNTS_DOWN
19 * Size of malloc() pool
21 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
23 #define CONFIG_PL011_CLOCK 150000000
24 #define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
26 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
28 #define CONFIG_MISC_INIT_R
29 #define CONFIG_SCSI_AHCI_PLAT
30 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
31 #define CONFIG_SYS_SCSI_MAX_LUN 1
32 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
33 CONFIG_SYS_SCSI_MAX_LUN)
35 #define CONFIG_CALXEDA_XGMAC
38 * Command line configuration.
41 #define CONFIG_BOOT_RETRY_TIME -1
42 #define CONFIG_RESET_TO_RETRY
45 * Miscellaneous configurable options
47 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
48 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
50 #define CONFIG_SYS_LOAD_ADDR 0x800000
51 #define CONFIG_SYS_64BIT_LBA
53 /*-----------------------------------------------------------------------
55 * The DRAM is already setup, so do not touch the DT node later.
57 #define CONFIG_NR_DRAM_BANKS 0
58 #define PHYS_SDRAM_1_SIZE (4089 << 20)
59 #define CONFIG_SYS_MEMTEST_START 0x100000
60 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000)
62 /* Environment data setup
64 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
65 #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
66 #define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */
67 #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
69 #define CONFIG_SYS_SDRAM_BASE 0x00000000
70 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000
71 #define CONFIG_SKIP_LOWLEVEL_INIT