1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the Renesas GRPEACH board
5 * Copyright (C) 2017-2019 Renesas Electronics
11 /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
12 #define CONFIG_SYS_CLK_FREQ 66666666
15 #define CONFIG_BAUDRATE 115200
18 #define CONFIG_SYS_PBSIZE 256
19 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
20 #define CONFIG_CMDLINE_TAG
21 #define CONFIG_ARCH_CPU_INIT
23 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
24 #define CONFIG_SYS_SDRAM_BASE 0x20000000
25 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
26 #define CONFIG_SYS_INIT_SP_ADDR \
27 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
28 #define CONFIG_SYS_LOAD_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
31 #define CONFIG_ENV_OVERWRITE 1
32 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
33 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
34 #define CONFIG_ENV_OFFSET 0x80000
37 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
38 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
41 #define CONFIG_BOOTARGS "ignore_loglevel"
43 /* Network interface */
44 #define CONFIG_SH_ETHER_USE_PORT 0
45 #define CONFIG_SH_ETHER_PHY_ADDR 0
46 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
47 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
48 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
49 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
50 #define CONFIG_BITBANGMII
51 #define CONFIG_BITBANGMII_MULTI
53 #endif /* __GRPEACH_H */