1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration settings for the Renesas GRPEACH board
5 * Copyright (C) 2017-2019 Renesas Electronics
11 /* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
15 /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
16 #define CFG_SYS_SDRAM_BASE 0x20000000
17 #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
19 /* Network interface */
20 #define CFG_SH_ETHER_USE_PORT 0
21 #define CFG_SH_ETHER_PHY_ADDR 0
22 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
23 #define CFG_SH_ETHER_CACHE_WRITEBACK
24 #define CFG_SH_ETHER_CACHE_INVALIDATE
25 #define CFG_SH_ETHER_ALIGNE_SIZE 64
27 #endif /* __GRPEACH_H */